The Xtensa 9 Processor for SOC Design

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Xtensa 9 Processor

Small, Ultra-Low-Power Dataplane Controller

Tensilica's Xtensa 9 DPU (dataplane processing unit) is a small, ultra-low-power controller built on Tensilica's unique Xtensa technology. It can easily be extended to out-perform any other embedded processor for a specific application using a combination of configurable options and custom instructions.

By embedding functionality right into the processor datapath itself, designers can use the Xtensa DPU to not only perform control functions, but also some of the finite state machine tasks that manage RTL blocks and some of the RTL functionality as well. This makes for a smaller, more efficient chip design, and it significantly reduces the verification challenges associated with new RTL designs.

Xtensa system diagram

Xtensa: a small, ultra-low-power embedded dataplane controller with direct connectivity to RTL for cycle-by-cycle deterministic control and data operations

Create an Optimized DPU in Minutes

The Xtensa processor is unlike other conventional embedded processors cores. The system designer can mold the Xtensa processor to fit the target application, instead of molding the application to fit the processor. By selecting and configuring predefined elements of the architecture and by inventing completely new instructions and hardware execution units, the Xtensa processor can deliver performance levels that are orders of magnitude faster than other 32-bit cores.Not only that, you can do this in a fraction of the time it takes to develop and verify an RTL-based solution.

Designers can define new instructions utilizing the Tensilica Instruction Extension (TIE) methodology, adding Verilog-like descriptions of datapaths, execution units, and register files that can deliver performance, area, and power characteristics approaching that of custom logic design.

Features

  • Highly efficient, small, ultra- low-power core with a 32-bit modern architecture and 5-stage pipeline
  • Wide range of configurable options
  • Local memories configurable up to 8MB with option for parity or ECC
  • Extend with application-specific instructions, execution units and register files
  • 32-bit wire input and 32-bit wire output GPIO port option for peripheral control and monitoring
  • 2x32-bit queue FIFO interface option for data streaming directly to RTl or other Xtensa processors
  • Optional floating point unit plus double-precision floating point acceleration
  • Wide range of operating system support including Linux
  • A complete software tool chain is automatically generated for each core


    • Benefits


    • Extremely efficient base architecture that is smaller, lower power, and has better code density than most other 32-bit embedded controllers
    • Application-specific instruction extensions provide orders of magnitude performance improvements over traditional CPUs, in many cases eliminating the need to develop RTL blocks
    • Lower verification effort with pre-verified, correct-by-construction, RTL generation
    • Post-silicon programmability to extend the life of any design
    • Highly accurate, high-speed system simulation models automatically created for software development.
    • Develop, simulate, debug and profile in one IDE


    Specifications

    Configuration Post-Route Area uM2) Clock Rate (MHz) Power Dissipation (mW/MHz)
    Smallest* - Synopsys library, TMSC 40LP, low-power flow 0.024 60 0.012
    Smallest* - Synopsys library, TSMC 40LP, high-speed flow 0.044 670 0.018
    Smallest* - Synopsys library, TMSC 45GS, low-power flow 0.024 62 0.009
    Smallest* - Synopsys library, TSMC 45GS, high-speed flow 0.044 1032 0.014
    106Micro** - Synopsys library, TSMC 40LP, low-power flow 0.046 57 0.017
    106Micro** - Synopsys library, TSMC 40LP, high-speed flow 0.074 540 0.026
    106Micro** - Synopsys library, TSMC 45GS, low-power flow 0.045 57 0.016
    106Micro** - Synopsys library, TSMC 45GS, high-speed flow 0.074 907 0.019

    *Smallest—smallest configuration used by customers with only local instruction and data RAM interfaces and full clock gating.

    **106Micro—similar to Tensilica’s Diamond Standard 106Micro with an iterative 32x32 multiplier, separate instruction and data memory interfaces, PIF, an interrupt controller with 15 interrupts at two priority levels, an integrated timer, on-chip debugging hardware, and embedded trace support.

    Xtensa Solution Diagram

    Processor solution

    Tensilica offers a complete solution for the Xtensa processor including automatically generated RTL and EDA scripts, system modeling and design support, Xtensa tools, and the software to optimize the processor for your application.

     

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