Xtensa 7 Processor Provides Fastest Customization Path, Lower Power and Advanced Security Provisions

Tensilica’s Xtensa 7 processor is a configurable, extensible and synthesizable 32-bit RISC processor core. The Xtensa 7 processor is extremely versatile - it is well suited for control-plane as well as data-plane SOC applications.

The Xtensa 7’s architecture was designed, from the start, to enable designers to tailor each implementation to match the application requirements for the target SOC. The total Xtensa solution provides a configurable microprocessor core that is quickly integrated with other system blocks and is easily adapted to the needs of today’s high-volume, high-performance embedded applications. The Xtensa processor core is particularly well suited for digital consumer, networking, office automation and wireless embedded SOC applications.

Features

• 32-bit synthesizable RISC architecture with 5-stage pipeline, 16/24-bit instruction encoding with modeless switching
• Designer-configurable processor options (MMU/MPU, local memory types and sizes, hardware multipliers, etc.)
• Optional designer-defined application-specific instructions can be added to the base architecture
• XPRES Compiler automates generation of instruction extensions from C/C++ algorithms
• Automated fine and coarse-grain clock gating for ultra-low power
• Local memories can include parity or ECC.

Benefits

• Extremely efficient base architecture that is smaller, lower power, and has better code density than other 32-bit processors
• Application-specific instruction extensions provide orders-of-magnitude application performance improvements, eliminating the need for RTL blocks from SOCs
• Pre-verified, correct-by-construction RTL generation lowers verification efforts
• Reduces design risk with post-silicon programmability using processors instead of RTL blocks.

Create an Optimized Processor in Minutes

By selecting and configuration predefined elements of the architecture and by inventing completely new instructions and hardware execution units, the Xtensa 7 processor can deliver performance levels orders of magnitude faster than standard 32-bit processor cores. Designers define new instructions utilizing the Tensilica Instruction Extension (TIE) methodology, adding Verilog-like descriptions of datapaths, execution units, and register files that can deliver performance, area, and power characteristics equivalent to custom logic design.

Or, the designer can use the XPRES Compiler to analyze the C/C++ algorithm and automatically suggest configuration options and extensions that will run that algorithm faster. Compared to traditional hardware design, Xtensa processors deliver similar quality of results with the added benefits of accelerated design time and post-silicon software programmability, making Xtensa 7 processors ideal choices for all complex SOC designs.

Profile the application software, configure the Xtensa core and add new instructions to optimize performance - all in a matter of minutes in Tensilica's Xtensa Xplorer design environment. Before committing to silicon, system designers can explore multiple architectures by making area, speed, power and code-density design tradeoffs based on real-time feedback from the Xtensa Xplorer environment. Then, the Xtensa Processor Generator automatically creates tailored, application-specific embedded processors quickly and reliably, to your exact specifications. Pre-verified, correct-by-construction RTL generation lowers verification efforts.

See a quick comparison to the Xtensa LX2 processor.

To learn more details about the Xtensa 7 processor solution, click About Xtensa.