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Out-of-the-Box EEMBC Benchmarks
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The What, Why and How of Configurable Processors
How to Increase ASICs and SOC Computational Performance with Long-Word Processors
Processor Ports and Queues: Easily Overcome I/O Bandwidth Obstacles in Your Next ASIC or SOC Design
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Processor Configuration with Chris Rowen
A Better Basic Architecture
The Xtensa Instruction Set Architecture (ISA) was designed from the ground up for embedded applications. With advanced architectural features such as a register-windowing scheme that accelerates function calls, and built-in zero-overhead loop capability to accelerate the repetitive inner code loops typically found in embedded computing applications, the Xtensa processor delivers superior performance in most embedded applications on ‘out of the box" application code. And for even better performance, see the results when the code was optimized.
The Proof
The EEMBC benchmarks prove it. EEMBC results include 2 types of performance testing – “out of the box" and “optimized." As the name implies, “out of the box" literally means taking the unadulterated benchmark C code – no code tuning, no assembly coding, no algorithm restructuring – and running it through a compiler and measuring the results. More detail on the exact configurations used are in the EEMBC overview.
The following chart compares EEMBC Out-of-the-Box benchmark performance for several licensable processor architectures on a per-MHz basis– a true and fair measure of pure ISA architectural strengths.
EEMBC "out of box" scores: Identical C source code compiled to target architectures. All scores simulated. Updated February 2003.
This optimized architecture is extremely efficient because of its very small code size.
See the results of the optimized benchmarks.
