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The Most Efficient Code Size
The Xtensa Instruction Set Architecture (ISA) employs a unique, patented, native 16-bit/24-bit instruction-encoding format. 16-bit instructions and 24-bit instructions are freely intermixed within an executable code set. Many of the most commonly used base processor instructions have both 16b and 24b formats, allowing significant code density improvements. And the full active register file window is addressable in both 16-bit and 24-bit instruction.
The Xtensa ISA seamlessly and modeliessly incorporates 16-bit instruction words that can be freely intermixed with 24-bit instructions to achieve higher code density without compromising application performance. The Xtensa 7 processor's instruction stream yields an average of 20 bits per machine instruction because more than 50% of the typical static instruction mix can use the 16-bit instruction format.
The Xtensa processor also has several compound instructions that reduce the instruction count required to encode and execute a program. Compare-and-branch instructions constitute the most important class of compound instructions. By itself, the compare-and-branch compound instruction class reduces code size by at least 5%. Other compound Xtensa instructions include shift (by 1-3 places), add/subtract, and shirt-and-max.
The Xtensa processor employs register windows to reduce the number of instruction bits needed to specify a register, resulting in substantial savings in code size.
Code Density without Negative Performance Impacts
The Xtensa ISA delivers code size improvements with no “mode switch" performance penalty and no loss of register addressing depth. Some competing architectures offer code density enhancements by recycling a desktop CPU architecture from the 1980s, evolving that non-embedded ISA into an “embedded processor architecture" by bolting on a 16-bit instruction mode. But mode switching often incurs a performance penalty of several clock cycles to switch modes, and several additional cycles to switch back, preventing the free intermixing of narrow and wide instructions and forcing tedious function-by-function iterative compilation to balance code size –vs- performance. Other 32-bit architectures suffer significant performance degradations when using 16-bit instructions because the full register file is not accessible, or only single operand instructions exist in the 16-bit mode.
As the chart below shows, the Xtensa processor offers low code size and high performance.
Proof: High Performance And Optimal Code Size
The EEMBC benchmarks prove that the Xtensa ISA delivers an unbeatable combination of performance and code density – at the same time.
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