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Xtensa Performance and Benchmarks
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The What, Why and How of Configurable Processors
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Processor Ports and Queues: Easily Overcome I/O Bandwidth Obstacles in Your Next ASIC or SOC Design
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Processor Configuration with Chris Rowen
Performance Leadership
Because it can be matched perfectly to your application, the Xtensa processor core is much faster than other 32-bit processors and rivals hand-coded RTL performance. Particularly when custom TIE instructions are added, the performance impact can be outstanding. Performance increases of 2x - 100x are common.
Specifications
| Configuration | Post-Route Area uM2) | Clock Rate (MHz) | Power Dissipation (mW/MHz) |
| Smallest* - Synopsys library, TMSC 40LP, low-power flow | 0.024 | 60 | 0.012 |
| Smallest* - Synopsys library, TSMC 40LP, high-speed flow | 0.044 | 670 | 0.018 |
| Smallest* - Synopsys library, TMSC 45GS, low-power flow | 0.024 | 62 | 0.009 |
| Smallest* - Synopsys library, TSMC 45GS, high-speed flow | 0.044 | 1032 | 0.014 |
| 106Micro** - Synopsys library, TSMC 40LP, low-power flow | 0.046 | 57 | 0.017 |
| 106Micro** - Synopsys library, TSMC 40LP, high-speed flow | 0.074 | 540 | 0.026 |
| 106Micro** - Synopsys library, TSMC 45GS, low-power flow | 0.045 | 57 | 0.016 |
| 106Micro** - Synopsys library, TSMC 45GS, high-speed flow | 0.074 | 907 | 0.019 |
Leading the Industry Benchmarks
The enhancements made to Xtensa, in particular to the XCC compiler, have enabled Tensilica to extend its lead in overall processor performance on two industry-standard benchmarks: EEMBC and Dhrystone.
In the EEMBC benchmark suite – an independently certified benchmark developed to measure the performance of processors in a variety of embedded applications – Tensilica posted the highest scores ever published for a processor core on the Network, Telecom and Office Automation tests.
Both “Optimized" and “Out of the box" configurations of Xtensa were tested. “Out of the box" tests measured the performance of cores using unmodified C-code, while “Optimized" tests measured the performance of Xtensa with modifications to the C code to utilize the TIE instruction extensions to optimize performance. No assembly coding was used in the EEMBC benchmarks, and no assembly coding is ever required to utilize the power of TIE extensions.
For more information on Tensilica’s EEMBC benchmarks, see:- Out of the Box scores explained
- Optimized scores explained
- Code size impact explained, and
- Background on Tensilica’s EEMBC testing.
Another universal yardstick for measuring processor performance is the Dhrystone benchmark (v2.1). The Xtensa 32-bit core outperforms processors from ARM and other companies on this benchmark, delivering 2.0 DMIPS/MHz with full optimization, and 1.2 DMIPS/MHz with no in-lining. For example, the ARM 1020E delivers 1.7 and 1.2 DMIPS/Mhz, respectively. All data current February 2003.
