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Innovative I/O Configuration Options
Product Briefs
White Papers
The What, Why and How of Configurable Processors
How to Increase ASICs and SOC Computational Performance with Long-Word Processors
Processor Ports and Queues: Easily Overcome I/O Bandwidth Obstacles in Your Next ASIC or SOC Design
Videos
Processor Configuration with Chris Rowen
Configuration Options Bypass the Bus for Fast, Efficient Data I/O
Tensilica offers two configuration click-box options that allow Xtensa processors to very quickly communicate data, control or status information with RTL blocks or other Xtensa processors.
The GPIO32 configuration option adds two 32-wire ports to the Xtensa processor (one input, one output) to quickly control and monitor peripherals or other logic in the system.
The QIF32 configuration option adds two 32-bit queue interfaces for FIFO-like data streaming into and out of the processor. The input queue functions with a familiar pop/empty/data interface to external logic while the output queue presents a similar push/full/data interface. All interactions with the Xtensa processor pipeline are automatically implemented when the option is selected.
These options are accessed as registers in the processor, so no separate load/store is required to operating on the data.
GPIO ports and queue interfaces allow direct data transfers for the fastest connections to RTL blocks or other Xtensa processors
The Xtensa LX4 DPUs offer even more flexible I/O options.
