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Xtensa Error Detection and Correction
Product Briefs
White Papers
The What, Why and How of Configurable Processors
How to Increase ASICs and SOC Computational Performance with Long-Word Processors
Processor Ports and Queues: Easily Overcome I/O Bandwidth Obstacles in Your Next ASIC or SOC Design
Videos
Processor Configuration with Chris Rowen
Soft Memory Error Detection and Correction
As process geometries continue to shrink, soft memory errors caused by alpha particle collisions with embedded memory cells increase due to lower cell capacitances and lower supply voltages.
Additionally, deep submicron, multi-million gate SOCs drive up the number of processors per chip, increasing the number of local, tightly coupled memories (cache, instruction and data memories). Each processor might have 4 or more local SRAMs, so the total bit count of local memories will grow rapidly.
Use Parity or ECC
Xtensa processors can be configured to detect or correct memory errors using either parity or ECC (Error- Correcting Code). Parity will generate an exception when a single-bit soft error is detected in the cache data array, cache tag array, or local memory (instruction and/or data memories).
ECC will correct single-bit errors and detect double-bit errors. Error correction is extremely important in storage and networking applications in mission critical applications where reliability and accuracy are a paramount concern. It is also very important in automotive applications to help meet error-free automotive safety standards.
