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Adding Instructions Through TIE - The Tensilica Instruction Extension Language
One of the fundamental technology innovations in the Xtensa processor is the ability to easily and seamlessly add new instructions into the processor's datapath. The associated C data types, software tool chain support and the EDA scripts required to synthesize the processor are all generated automatically, just as if they had been there from the start. The specification of this new datapath and associated instructions and C data types is written in the Tensilica Instruction Extension (TIE) language.
Most embedded processors offer fixed hardware functionality with options for memory size, cache size, and bus interface. Performance is proportional to the clock speed. Beyond that, application code optimization effort or a move to the next processor in the roadmap is required. Tensilica offers something different-the opportunity to optimize the processor itself using Tensilica's TIE language.
Tensilica's TIE language is used to describe new instructions, registers and execution units that are then automatically added to the Xtensa processor. TIE is a Verilog-like language used to describe desired instruction mnemonics, operands, encoding, and execution semantics. The TIE files are inputs to the Xtensa Processor Generator. The Generator automatically builds the processor and the complete software tool chain that incorporates all configuration options and new TIE instructions. The base instruction set remains for maximum compatibility with third party development tools and operating systems.
The TIE language unlocks the true power of the Xtensa processor. It allows designers to get orders of magnitude performance increases in their processors and create differentiated processors.
Flexibility to Add Just What You Need
Just as the designer can choose from a set of predefined functional options to improve processor performance, the designer can now create instructions that can speed up standard or proprietary algorithms. Using the tools provided, application hot spots can be identified and additional logic created to process these hot spots more efficiently, without the need to increase the clock frequency or re-write the software.
Differentiate-Make a Processor That's Uniquely Your Own
When processors have fixed hardware functionality and your competitors are using the same or similar processors, then differentiation is often limited to the algorithm implemented. Fixed processors are good at general-purpose computing, but not so good at any specific algorithm. Tensilica gives you the opportunity to differentiate at the hardware level and implement algorithms more efficiently by designing hardware that will accelerate your specific algorithm. This means that your design will be almost impossible to copy, as only your hardware will reach the performance required on the same software implementation.
Make Changes, Feel Safe
Configurability of a Tensilica processor core never compromises the underlying base Xtensa instruction set architecture (ISA), thereby ensuring availability of a robust ecosystem of third party application software and development tools. All configurable, extensible Xtensa processors are always compatible with major operating systems, debug probes, and ICE solutions. For each processor, the automatically generated complete software development toolchain includes an advanced Integrated Development Environment (IDE) based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry standard GNU Toolchain.
Tensilica uses an ISA that has been backwards compatible since its introduction in 1999. It uses a base instruction set of 80 instructions and was fundamentally architected for extensibility. Designers can run application code written back in 1999 and it will run on the Xtensa processor today. Any differentiating designer-defined instructions from earlier designs can be re-used today.
What Can You Do With TIE?
The TIE language can describe new registers, register files, and custom data types – such as 24-bit data for audio applications, 56-bit data for security processing, 256-bit data types for packet processing – whatever your application requires. Why create odd-sized data types and registers? Matching register sizes to the corresponding data types saves area and power (by eliminating unused bits) Further, a custom-designed register file and special single-cycle instructions can efficiently handle DES encryption algorithms (for example) while a rigid processor core with a fixed instruction set might take 20 or 40 or more cycles.
A designer creates a TIE file defining new functions and data types using the TIE development and analysis tools in Xtensa Xplorer. The TIE file can be used with the TIE compiler to create updated software tools and instruction set simulator within minutes, on the desktop. Try this with other configurable processors, and you’ll have to integrate new instructions manually over a span of several weeks.
How the Customization Process Works
When you want to build the whole core and RTL, turn to the Xtensa Processor Generator. In minutes, the Xtensa Processor Generator automatically builds a correct-by-construction RTL (register transfer level) description of the Xtensa processor that includes all the newly described functions and resources, as well as a complete software tool suite that incorporates the new TIE instructions, registers, and data types. Because the processor and software development tool suite are generated from one source description and a common database, the software development tools track the processor hardware and there is no possibility of a mismatch. Tensilica is the only company to offer this level of risk-free automation for configurable and extensible processors.
The Xtensa Automated Customization Process
Higher-Level TIE Syntax
Designers can specify new instructions at a much more abstract level, whicih makes it much easier to experiment with different Xtensa processor configurations using Xtensa Xplorer. The higher-level syntax describes a potential new instruction without first needing to explicitly defining details such as opcode encoding or operand encoding, and without fully specifying the detail of the functional implementation or the details of user-defined register files and state variables. Tensilica’s TIE Compiler can automatically determine the optimal instruction encodings and implementation in minutes using a process that “maps" the abstract instruction definition into a detailed implementation description.
This higher-level TIE syntax has several benefits:
- Faster exploration of custom instruction ideas
- Significantly easier re-use
- Significantly easier to combined “solution packages" from multiple creators,within companies and from third party providers.
See more about the TIE language.
Read more about accelerating existing application code.
Read more about designing SOC hardware using task engines based on Xtensa processors instead of HDL-based logic blocks.
Read more about the TIE Compiler.
EEMBC Benchmarks - TIE Results in Excellent Optimized Scores
The results are in. Adding TIE instructions provide optimized scores better than any other embedded processor. Check out the results.
