Configurability

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Build Processors Tailored to Your Application

Tensilica's ISA was fundamentally archiected for configurability and extensibility. It starts with a foundation instruction set with 80 instructions. We make it easy to customize the processor with several configuration options, which are presented either as check-box options or drop-down menus.

Each instance of the Xtensa processor core is unique to the designer who creates it. Applications are not locked into a set of features that were predetermined years or decades earlier by a processor designer.

Configurability of a Tensilica processor core never compromises the underlying base Xtensa instruction set, thereby ensuring availability of a robust ecosystem of third party application software and development tools. All configurable, extensible Xtensa processors are always compatible with major operating systems, debug probes and ICE solutions; and always come with an automatically generated, complete software development toolchain including an advanced integrated development environment based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry-standard GNU toolchain.

Basic Interface Options
  • Processsor interface (PIF) width: 32/64/128-bits
  • Optional "no PIF" configuration
  • Optional AMBA AXI and AHB-lite bridges with synchronous or asynchronous clocking
  • Optional 16-bit processor ID
  • Inbound DMA option
  • XLMI high-speed local interface
  • Big-Endian/little-Endian byte ordering
  • On-chip debug port (IEEE 11.49.1)
  • Trace port signals
  • Up to 32 interrupts with up to 7 levels of priority plus a separate non-maskable interrupt level
  • 2x32-wire GPIO ports for direct control and monitoring of peripherals
  • 2x32-bit queue interfaces for streaming data into and out of the processor via FIFOs
  • Single 16-bit MAC (multiply accumulator)
  • 16- or 32-bit multipliers
  • Low-area integer divider
  • Single-precision floating point unit
  • Double-precision floating point accelerator
Memory subsystem options
  • Up to 2 local instruction and data RAMs and ROMs up to 8 Mbytes each
  • Local data and instruction caches:
    • Up to 4-way set associative
    • Up to 32 KB
    • Write-back and write-through cache write policy
  • 4-way cache plus local memories
  • Region protection
  • Region protection with translation
  • Memory Management Unit (MMU) with Translation Look Aside Buffers (TLBs), includes no-execute bit security support
  • MMU for the Linux Operating System
Design support
OS support
  • Express Logic's ThreadX OS
  • Open source Linux. NOTE: See Tensilica's open-source Linux website.
  • Mentor's ATI Nucleus Plus
  • Micrium's uC/OS II
  • Tata Elxsi's Ro-SES

 

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