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A Better Basic Architecture
The Xtensa Instruction Set Architecture (ISA) was designed from the ground up for embedded applications. With advanced architectural features such as a register-windowing scheme that accelerates function calls, and built-in zero-overhead loop capability to accelerate the repetitive inner code loops typically found in embedded computing applications, the Xtensa processor delivers superior performance in most embedded applications on ‘out of the box" application code.
The Xtensa 32-bit architecture features a compact instruction set optimized for embedded designs. The base architecture has a 32-bit ALU, up to 64 general-purpose physical registers, six special purpose registers, and 80 base instructions, including improved 16- and 24-bit (rather than 32-bit) RISC instruction encoding. Key features include:
- A wide range of configurable options to ensure you get just the logic you need to meet your functional and performance requirements
- Modelessly intermix 16- or 24-bit instructions for lowest code and performance overhead.
- Efficient 5-stage pipeline
- Local memories configurable up to 4MB with optional parity or ECC
- Caches up to 32KB and up to 4-way set associativity on both Instruction and Data sides
- Automated fine-grained clock gating throughout processor for ultra-low power solutions
Base Instruction Set Compatibility
Configurability of a Tensilica processor core never compromises the underlying base Xtensa instruction set architecture (ISA), thereby ensuring availability of a robust ecosystem of third party application software and development tools. All configurable, extensible Xtensa processors are always compatible with major operating systems, debug probes, and ICE solutions. For each processor, the automatically generated complete software development toolchain includes an advanced Integrated Development Environment (IDE) based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry standard GNU Toolchain.
Tensilica uses an ISA that has been backwards compatible since its introduction in 1999. It uses a base instruction set of 80 instructions and was fundamentally architected for extensibility. Designers can run application code written back in 1999 and it will run on the Xtensa processor today. Any differentiating designer-defined instructions from earlier designs can be re-used today.
Smaller Code Size
The Xtensa DPU can modelessly issue 24-bit and 16-bit instructions, leading to 25-50% better code density and, therefore, smaller memories than mixed 32- and 16-bit architectures. Since memories typically dominate SOC area, this code density advantage translates into significant SOC area savings.
Powerful Base ISA
The Xtensa ISA includes powerful compare-and-branch instructions and zero-overhead loops, which allow the compiler to generate tight, optimized loops. It also provides bit manipulations including funnel shifts and field-extract operations that are critical for applications such as networking that process the fields in packet headers and perform rule-based checks.
Extensible ISA
One of the fundamental technology innovations in the Xtensa processor is the ability to easily and seamlessly add new instructions into the processor's datapath. The associated C data types, software tool chain support and the EDA scripts required to synthesize the processor are all generated automatically, just as if they had been there from the start. The specification of this new datapath and associated instructions and C data types is written in the Tensilica Instruction Extension (TIE) language, which is explained in more detail in a later section.
The Proof
The EEMBC benchmarks prove it. EEMBC results include two types of performance testing – “out of the box" and “optimized. As the name implies, “out of the box" literally means taking the unadulterated benchmark C code – no code tuning, no assembly coding, no algorithm restructuring – and running it through a compiler and measuring the results.
The following chart compares EEMBC Out-of-the-Box benchmark performance for several licensable processor architectures on a per-MHz basis– a true and fair measure of pure ISA architectural strengths.
EEMBC "out of box" scores: Identical C source code compiled to target architectures. Xtensa optimized scores are 4X to 23X faster. Simulated scores except NEC
This optimized architecture is extremely efficient because of its very small code size.
Read our Xtensa Architecture White Paper.
