Xtensa Feature Summary

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A World-Class Processor Core

The Xtensa 32-bit architecture features a compact instruction set optimized for embedded designs. The base architecture has a 32-bit ALU, up to 64 general-purpose physical registers, 6 special-purpose registers and 80 base instructions, including improved 16- and 24-bit (rather than 32-bit) RISC instruction encoding.

The Xtensa CPU implements the proven Xtensa instruction set architecture (ISA), which enables designers to achieve significant code size reductions compared to conventional RISC cores. Reducing code size results in higher performance and better power dissipation - key to saving cost in highly integrated SOC designs. The Xtensa ISA's 16- and 24-bit encoding also provides powerful branch instructions and zero-overhead loops, and bit manipulations including funnel shifts and field-extract operations.

Configurability of a Tensilica processor core never compromises the underlying base Xtensa instruction set, thereby ensuring availability of a robust ecosystem of third party application software and development tools. All configurable, extensible Xtensa processors are always compatible with major operating systems, debug probes and ICE solutions; and always come with an automatically generated, complete software development toolchain including an advanced integrated development environment based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry-standard GNU toolchain.

Backwards compatible ISA since 1999:

  • Fundamentally architected for extensibility
  • Base instruction set of 80 instructions
  • Run application code written back in 1999
  • All optional blocks are still available
  • Any differentiating designer-defined logic can be re-used today

Optional pre-defined execution units:

  • 32-bit multiplier and/or 16-bit multiplierand MAC
  • Integer divide
  • Floating-point unit
  • Double-precision floating-point acceleration

Differentiate with designer-defined functions:

  • Make your specific algorithm run even more efficiently by adding the instructions it needs
  • Development tools automatically adapt for full support

Natural connectivity with RTL blocks:

  • 2X32-wire GPIO ports for peripheral contorl and monitoring
  • 2x32-bit queue interfaces to FIFOs for data streaming into and out of the processor
  • Co-simulation with RTL down to the pin level with SystemC

Highly configurable interfaces:

  • Choice of 32-, 64- or 128-bit wide processor interface (PIF) to system bus
  • "No PIF" configuration option
  • Hardware prefetch unit
  • Optional high-speed Xtensa Local Memory Interface (XLMI)
  • Write buffer: selectable from 1 to 32 entries
  • Optional AMBA AXI and AHB-Lite bridges with synchronous or asynchronous clocking
  • Choice of 1-, 2- or 4-way cache and/or local memories
  • Up to 32 interrupts

Multiple processor design support:

  • Multi-core system modeling and SystemC: co-simulation out-of-the-box, fully supported within the Xtensa Xplorer IDE
  • Homogeneous and heterogeneous subsystems supported
  • Inter-core on-chip debug with break-in/out control
  • Optional 16-bit processor ID
  • Conditional store option and synchronization library provide shared memory semaphore operations and the "release consistency model" of memory access ordering

Complete hardware implementation and verification flow support:

  • Automatic generation of RTL and tailored EDA scripts for leading-edge process technologies, including physical synthesis and 3D extraction tools
  • Auto-insertion of fine-grained clock gating for ultra-low power
  • Hardware emulation support including automated FPGA netlist implementation
  • Comprehensive diagnostic test bench
  • Formal verification support for designer-defined functions

High-speed, high-accuracy system simulation models automatically created:

  • High-speed instruction-accurate simulator for software development
  • Pipeline-modeling, cycle-accurate Xtensa instruction set simulator
  • Xtensa SystemC (XTSC) transaction-level modeling (TLM) support, including out-of-the-box multi-core simulation
  • Hardware co-simulation with RTL in SystemC with Tensilica's pin-level XTSC

Integrated development environment:

  • Create, simulate, debug and profile whole designs in one tool - Xtensa Xplorer is a high productivity IDE
  • Ninth generation software development tools target each processor. The advanced Xtensa C/C++ compiler (XCC) includes optimizations for base, optional and designer-defined instructions.
  • Increase productivity with multi-core subsystem design and simulation support
  • Custom data display formatting for easy debug of vector and fixed-point data types as well as bit-mapped status and control.
  • Use Mentor Graphics Nucleus+, Express Logic's ThreadX, Micrium's uC/OS-II, http://www.linux-xtensa.org/, or Tata Elxsi's Ro-SES operating systems

Performance Summary

Processor architecture:

  • High-performance 32-bit RISC with 5-stage pipeline

Instruction set:

  • Xtensa ISA with compact 16-bit and 24-bit base instruction set
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