Xtensa Architecture

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An Instruction Set Architecture Designed for Embedded Applications

The Xtensa instruction set architecture (ISA) is a patented, modern processor core architecture designed for embedded SOC applications. The Xtensa 32-bit architecture features a compact 16- and 24-bit instruction set, with modeless switching, optimized for embedded designs.

The base architecture has 80 RISC instructions and includes a 32-bit ALU, up to 64 general-purpose 32-bit registers employing a register-windowing scheme that accelerates function calls and 6 special-purpose registers.

The Xtensa processor’s advanced architecture and compact instruction set allows designers to achieve significant code size reductions that result in higher code density and better power dissipation – key to saving cost in a highly integrated SOC ASIC.

The Xtensa ISA includes powerful branch instructions such as combined compare-and-branch and zero-overhead loops, and bit manipulations including funnel shifts and field-extraction operations. The Xtensa architecture also includes an optional floating-point unit and double-precision floating point acceleration..

Xtensa Architecture

The Xtensa Architecture

Lots of configurable building blocks:

  • Configurable function blocks are elements parameterized by the system designer.
  • Optional function blocks indicate elements available to accelerate specific applications.
  • Optional and configurable blocks are optional elements scalable to fit applications, including peripherals.
  • Advanced designer-defined functions are hardware execution units and registers added to the processor by the designer to accelerate specific algorithms for a given SOC design.

Common in all configurations is the base Instruction Set Architecture. For more information on the Xtensa ISA, download the PDF of the Xtensa ISA databook.

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