Xtensa LX Features

Product Briefs

Xtensa 9 Product Brief

Xtensa LX4 Product Brief

Articles

Microprocessor Report's review of Xtensa LX3

White Papers

Processor Ports and Queues: Easily Overcome I/O Bandwidth Obstacles in Your Next ASIC or SOC Design

How to Increase ASICs and SOC Computational Performance with Long-Wod Processors

Minimize Energy Consumption While Maximizing ASIC and SOC Performance

See entire white paper library

Videos

Processor Configuration with Chris Rowen

Enhance Your Application with a Click of the Mouse

Select from click-box options to add functionality to your processor and evaluate performance improvements in a matter of minutes. Or you can create TIE to add your own efficient instructions to the processor.

Xtensa LX4 Offers a Wide Range of Pre-Verified Click-Box Options to Simplify Design

Basic Interface Options:

• Processor interface (PIF)
  • Width: 32/64/128-bit
  • Optional "no PIF" configuration
• Optional AMBA AXI and AHB-Lite bridges with synchronous or asynchronous clocking
• Inbound DMA option
• XLMI high-speed local interface
• Big-Endian/Little-Endian byte ordering
• Choice of 1 or 2 general-purpose load/store units, each 32-, 64-, 128-, 256-, or 512-bits wide
• On-chip debug port (IEEE 1149.1 compliant)
• Trace port signals
• Up to 32 interrupts with up to 7 levels of priority plus a separate Non-Maskable Interrupt level
• Write buffer: selectable from 1 to 32 entries
• Multiple custom width GPIO ports for direct control and monitoring of peripherals
• Multiple custom width queue interfaces for streaming data into and out of the processor via FIFOs
• Single 16-bit MAC (multiply accumulator)
• 16- or 32-bit multipliers
• Low-area integer divider
• Single precision floating point unit
• Double precision floating point accelerator
• Optional AMBA AXI and AHB-Lite bridges with synchronous or asynchronous clocking
• Designer-defined Queues, Ports, and Lookups
• Optional 16-bit processor ID
• Support of 32-, 64- or 128-bit wide FLIX instructions

Memory Subsystem Options:

• 7-stage pipeline option
• Local data and instruction caches
  • Up to 4-way set associative
  • Up to 32 KB
  • Write-back and write-through cache write policy
• Memory management options
• Region protection
• Region protection with translation
• Memory Management Unit (MMU) with Translation Look Aside Buffers (TLBs), includes no-execute bit security support
• MMU for the Linux operating system
• Up to 6 local memory banks can be connected for instruction and data accesses (up to 12 in total). Memory banks may be local ROM, RAM or cache ways.
• Hardware prefetch for reducing long memory latencies
• Local data and instruction memories up to 8 MBytes
• Optional parity or ECC for all local memories