Products
Xtensa LX as an RTL Companion
Product Briefs
Articles
Microprocessor Report's review of Xtensa LX3
White Papers
Processor Ports and Queues: Easily Overcome I/O Bandwidth Obstacles in Your Next ASIC or SOC Design
How to Increase ASICs and SOC Computational Performance with Long-Wod Processors
Minimize Energy Consumption While Maximizing ASIC and SOC Performance
See entire white paper library
Videos
Bandwidth of Hard-Wired Logic and Performance without Hand-Coded State Machines
RTL verification has become the most resource and time consuming aspect of SOC design. The Xtensa LX4 processor offers unique advantages as an addition to your own hardwired RTL blocks in complex SOCs. The Xtensa LX4 can connect directly to your RTL with dedicated high bandwidth data and control interfaces.
The Xtensa LX4 processor can achieve virtually the same levels of inter-block I/O bandwidth and intra-block computational parallelism as hard-wired logic designed with traditional RTL design methodologies. How? By using a combination of TIE Ports and Queues, parallel FLIX execution units, and some TIE instructions.
Unlike RTL-based designs, Xtensa LX4 processors are pre-verified, and do not require hard-wired implementation of complex state machines. Instead of state machines, the complex data-paths added to Xtensa LX cores are sequenced and controlled by the processor's instruction stream. That means the "control logic" is fully programmable and can be debugged using software development methodologies - reducing verification time and risk for the entire SOC.
Lower Verification Effort and Time
Designing hardwired RTL blocks has become more about verification than about design. Design teams typically spend twice the number of resources and person months on verification than on design. Design changes made late in the project cycle are often limited by the verification effort.
Typically, 90% of the RTL block's area lies in the datapath and only 10% in the control logic, yet most (perhaps 90%) of the bugs are found in the control logic. The ability to extend the Xtensa LX processor using TIE enables designers to create datapaths inside the Xtensa processor without the need to generate and verify the assocated control logic. Instead the control logic is expressed in software as instructions that execute on the processor.
It is easier to verify TIE extensions made to the Xtensa LX processor than it is to verify an equivalent RTL data path, since only the input-output relationship and functional behavior of the operations specified in TIE have to be verified. The TIE Compiler and Xtensa Processor Generator take care of converting the TIE specification into data path elements in the processor pipeline and implementing the control, decode, and bypass logic in the processor control units.
Reuse of the Same Hardware for Multiple Tasks
Complex SOCs consist of millions of gates of logic and are designed to perform multiple tasks. Often these multiple tasks do not need to be performed at the same time. This provides an opportunity for multiple tasks to share the same hardware units. Processors are particularly amenable to enabling this type of sharing.
Designers can specify a datapath in TIE that consists of a set of execution units that can be used by multiple tasks and then use the programmability of the processor to determine which tasks are executed. For example, an audio engine can be designed to implement a range of audio codecs, such as MP3, AC-3, WMA, etc.
Flexibility to Fix and Upgrade Algorithms Post Silicon
Using an Xtensa LX processor to implement an algorithm lets the designer fix, enhance and tweak the algorithm close to and after the SOC has taped out. In particular, post-silicon bugs now have a chance of being worked around.
Algorithms that are a subject for continuous research, such as half-toning in printers and image and video post processing, are ideal candidates for implementation in an Xtensa LX processor.
When new and updated standards emerge, such as for audio and video processing, they will likely run on your existing hardware because it is programmable.
Co-Simulation at the RTL Pin Level
Connect directly to your RTL wires using pin-level XTSC SystemC model interfaces without the need to purchase additional EDA vendor tools. This enhancement to transaction-level XTSC models allows designers to interchange SystemC and RTL blocks for co-simulation. This works with all of the major EDA vendor simulation tools.
Extending the Life of an Existing RTL Design
You can easily add functionality to an existing design, or upgrade parts of it for the latest standard, with limited development effort by using Xtensa LX DPUs.
A Conventional Processor SOC with RTL
With any other 32-bit processor core, all communication is through the system bus, which must have the available data bandwidth and must keep bus latency manageable.
Add New Functionality with Xtensa LX DPUs
With Xtensa LX, data can be kept off the system bus by using direct connectivity to RTL through Ports and Queues. These provide almost unlimited bandwidth with precise latencies.
When extending the functionality of existing RTL blocks, the control logic parts can be brought into the Xtensa LX to make the FSM easier to debug and verify.
When larger changes to the datapath are needed, then the whole RTL function can be brought into the Xtensa LX processor.
