Xtensa Configurable Processors

Configure Processors to Match Your Application

You don't need to be locked into a set of features that were predetermined years of decades earlier by a processor designer. You can configure your Xtensa processor to exactly match your application.

Not sure exactly what options you need? You can use our Xtensa Xplorer IDE to evaluate trade-offs. This section explains some of the tools we have that can help you make intelligent decisions about options such as memory types and sizes, interface options and other execution unit and ISA options.

Configurability of a Tensilica processor core never compromises the underlying base Xtensa instruction set, thereby ensuring availability of a robust ecosystem of third party application software and development tools. All configurable, extensible Xtensa processors are always compatible with major operating systems, debug probes and ICE solutions; and always come with an automatically generated, complete software development toolchain including an advanced integrated development environment based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry-standard GNU toolchain.

See How Easy It Is to Configure an Xtensa Processor

See our CTO, Chris Rowen, in action, configuring a processor right before your very eyes.

Check Box Configuration Options

It's as easy as checking a box to pick the options for your application. The Xtensa Processor Generator allows quick configuration of many Xtensa core options using simple clock-box screens, including:

Basic Configuration Options

• Processor interface (PIF)
  • Width: 32/64/128-bit
  • Optional “no PIF" configuration
• Inbound DMA option
• XLMI high-speed local interface
• Big-Endian/Little-Endian byte ordering
• On-chip debug port
• Trace port signals
• Up to 32 interrupts
• Write buffer: selectable from 1 to 32 entries
• Single 16-bit MAC
• 16- or 32-bit multipliers
• Low-area integer divider
• Single-precision floating point unit
• Double=precision floating point accelerator
• Designer-defined Queues (FIFO interfaces), Ports (GPIOs) and Lookups
• Optiional AMBA AXI bridge or AMBA AHB-lite bridges with synchronous or asynchronous clocking

Sample Configuration Screen

Memory Subsystem Options

• Memory management options include region protection, region protection with translation, and Memory Management Unit (MMU) with Translation Look Aside Buffers (TLBs), including no-execute bit security support for the Linux operating system. See Tensilica's open-source Linux website.
• Up to 2 local instruction and data RAMs and ROMs up to 8 Mbytes each
• Local Data and Instruction Caches
  • Up to 4-way set associative
  • Up to 32 KB
  • Write-back and write-through cache write policy
• Region protection
• Region protection with translation
• Optional parity or Error Correcting Code (ECC)