Products
Xtensa Configurable and Extensible Processors
Product Briefs
Articles
Microprocessor Reports' December 2009 review of Xtensa LX3 and Xtensa 8
White Papers
The What, Why and How of Configurable Processors
How to Increase ASICs and SOC Computational Performance with Long-Word Processors
Processor Ports and Queues: Easily Overcome I/O Bandwidth Obstacles in Your Next ASIC or SOC Design
Videos
Processor Configuration with Chris Rowen
Get Orders of Magnitude Performance Increases
It's easier and faster to add new instructions to an Xtensa processor than to design a Verilog hardware block to perform that function. You can express the desired functionality in the Tensilica Instruction Extension (TIE) language. TIE is a Verilog-like language used to describe desired custom instructions. You can also specify that a complex instruction be implemented as a multi-cycle instruction with a single TIE language directive. TIE helps you get orders of magnitude performance increases out of your processor design.
EEMBC Benchmarks - TIE Results in Excellent Optimized Scores
The results are in. Adding TIE instructions provide optimized scores better than any other embedded processor. Check out the results.
With Complete Ecosystem and Tool Set
Adding TIE instructions to a Tensilica processor core never compromises the underlying base Xtensa instruction set, thereby ensuring availability of a robust ecosystem of third party application software and development tools. All configurable, extensible Xtensa processors are always compatible with major operating systems, debug probes and ICE solutions; and always come with an automatically generated, complete software development toolchain including an advanced integrated development environment based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry-standard GNU toolchain.
The TIE language can describe new registers, register files, and custom data types – such as 24-bit data for audio applications, 56-bit data for security processing, 256-bit data types for packet processing – whatever your application requires. Why create odd-sized data types and registers? Matching register sizes to the corresponding data types saves area and power (by eliminating unused bits) Further, a custom-designed register file and special single-cycle instructions can efficiently handle DES encryption algorithms (for example) while a rigid processor core with a fixed instruction set might take 20 or 40 or more cycles.
A designer creates a TIE file defining new functions and data types using the TIE development and analysis tools in Xtensa Xplorer Processor Developers Edition (Xplorer-PDE). The TIE file can be used with the TIE compiler to create updated software tools and instruction set simulator within minutes, on the desktop. Try this with other configurable processors, and you’ll have to integrate new instructions manually over a span of several weeks.
When you want to build the whole core and RTL, turn to the Xtensa Processor Generator. In minutes, the Xtensa Processor Generator automatically builds a correct-by-construction RTL (register transfer level) description of the Xtensa processor that includes all the newly described functions and resources, as well as a complete software tool suite that incorporates the new TIE instructions, registers, and data types. Because the processor and software development tool suite are generated from one source description and a common database, the software development tools track the processor hardware and there is no possibility of a mismatch. Tensilica is the only company to offer this level of risk-free automation for configurable and extensible processors.
Accelerate C Code, No Assembly Programming Required
Find out more about how you can accelerate existing C code using TIE, with no assembly programming required.
Learn about the benefits of designing in TIE rather than RTL.
Full Extensibility with TIE and Xtensa LX4
While you can use TIE with both Xtensa 9 and Xtensa LX4, you can take full advantage of the many unique features with our top-of-the-line full-featured Xtensa LX4 with TIE. TIE offers a wide range of flexibility in adding multi-cycle, pipelined execution units, register files, state registers, SIMD arithmetic and logic units, creating wide (up to 512-bit) load-store instructions, and adding designer-defined I/O Ports, Queues (FIFO interfaces), and Lookup interfaces. These powerful, advanced capabilities are not available in the Xtensa 9 processor.
