Automatically Generate Processors from Standard C Code

The Tensilica XPRES (Xtensa PRocessor Extension Synthesis) Compiler is a powerful TIE language synthesis tool that creates tailored Xtensa processors from native C/C++ code. You can use the XPRES Compiler, coupled with Tensilica’s proven Xtensa Processor Generator technology, to generate highly optimized processor hardware RTL directly from the C/C++ reference code or algorithmic specifications, eliminating the need to have an intimate knowledge of TIE.

XPRES enables the rapid development of optimized SOC hardware blocks and associated software tools. You can input the original algorithm into the XPRES compiler, written in standard ANSI C/C++, and the XPRES compiler automatically determines which functions should be accelerated in hardware.

Various area, performance, and power trade-offs can be quickly evaluated using the graphical output from the XPRES Compiler. The XPRES Compiler automates the analysis and creation of TIE descriptions, dramatically shortening the design time needed to transform an algorithmic concept into an optimized, pre-verified, software-programmable hardware element.

Xtensa Xplorer dramatically shortens the design time to speed up critical algorithms.

Automated Processor Optimization without C Code Modifications

The XPRES compiler works with the Xtensa XCC compiler to analyze the performance critical regions of your application software or algorithm specification. The XPRES Compiler uses this analysis information to generate one or more alternative TIE files designed to increase the performance of your code. The generated TIE files represent a range of customized Xtensa processors that trade-off improvements in application
performance versus hardware (area) costs.

The new TIE instructions and registers generated by the XPRES Compiler are utilized automatically when your original program or any other program is recompiled. No source code modifications are required. Also, since the XPRES Compiler creates TIE source files, the system designer is free to modify the TIE for further optimizations.

Optimized Hardware Directly from Source C Code

The C programming language is the natural language of choice for algorithm developers and systems architects to capture and model system behavior. For more than a decade, the embedded design industry has struggled to find a path that takes those C specifications of algorithms and automatically or systematically transforms them into efficient hardware designs. A variety of approaches - with buzzwords like behavioral synthesis, C language hardware synthesis, and ESL - have fallen short because they all have tried to conquer a nearly intractable problem - transforming a language designed to be executed in a sequential manner on a microprocessor into a highly parallel system of interoperating, non-programmable hardware elements.

Tensilica’s XPRES Compiler takes a different approach. The XPRES Compiler does not transform the C code. It automatically tailors the Xtensa microprocessor into an efficient machine that executes the original C code faster. The tailoring process takes only minutes.

Using the XPRES Compiler, designers often find that the automatically generated Xtensa processor is fast enough to meet their system’s specifications. In other cases, engineers can further extend the processor with custom I/O ports (Xtensa LX2 only) and custom execution units to get even higher performance.

The XPRES Compiler automates the creation of extensions for
Tenslica’s Xtensa processors. It works with Tensilica’s proven
Xtensa Processor Generator technology to rapidly create optimized hardware blocks for advanced SOC designs.

Automated Processor Optimization without C Code Modifications

The XPRES compiler works with the Xtensa XCC compiler to analyze the performance critical regions of your application software or algorithm specification. The XPRES Compiler uses this analysis information to generate one or more alternative TIE files designed to increase the performance of your code. The generated TIE files represent a range of customized Xtensa processors that trade-off improvements in application
performance versus hardware (area) costs.

The new TIE instructions and registers generated by the XPRES Compiler are utilized automatically when your original program or any other program is recompiled. No source code modifications are required. Also, since the XPRES Compiler creates TIE source files, the system designer is free to modify the TIE for further optimizations.

Performance acceleration versus hardware cost trade-off analysis

Rapid Design with Full Automation for Fine-Tuned Manual Control

For small algorithmic kernels, the XPRES Compiler performs exploration of potential configuration in just minutes. For very large application programs, such as full video codecs, the XPRES Compiler can explore millions of potential combinations of processor configurations in less than an hour. This very rapid exploration allows the system designer to quickly and exhaustively explore a variety of both automatically generated as well as manually generated TIE techniques.

In addition, the XPRES Compiler offers a range of fine-tuning control options fully integrated into the Xtensa Xplorer design environment.. The designer can exercise as much or as little intervention as desired into where and how optimization techniques are employed to create the optimal design of an application-specific Xtensa processor.
Read the XPRES white paper: Rapid SOC Development using Automatically Generated Processors.