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Accessed Through Xtensa Xplorer

One Common Platform for Processor Customization

Xtensa Xplorer is the only SOC design environment that integrates software development, processor optimization and multiple-processor system-on-chip (SOC) architecture tools into one common platform. Xplorer adds automation tools to the design process that make creating Xtensa processor-based SOC hardware and software much easier.

Xplorer serves as a cockpit for basic design management, invocation of Tensilica processor configuration tools (Xtensa Processor Generator, TIE Compiler, and XPRES Compiler) and software development tools (C/C++ toolchain, project management, and performance analysis).

Xtensa Xplorer is particularly useful for the development of TIE (Tensilica Instruction Extension) instructions that maximize performance for a particular application. TIE instructions can be created automatically from C/C++ code using the XPRES Compiler or they can be created by the design team. Different Xtensa processor and TIE configurations can be saved, profiled against the target C/C++ software, and compared. Xtensa Xplorer even includes automated graphing tools that create spreadsheet-style comparison charts of performance.

Complete RTL Source and Software Tools

The Xtensa Processor Generator - running on Tensilica's secure servers - builds the complete processor core and the tailored design tools. Processor and software tool suite generation takes only a few minutes. After downloading the newly created processor core and associated tools, the designer starts to develop the SOC with a unique processor, specifically tailored and matched to the assigned processing task. The resulting SOC will not have the same commodity core used by competitors. It’s an optimized processor, specific to one company’s SOC. If the designer needs to adjust the processor configuration for additional tuning, the turnaround time for a new processor is literally a matter of hours.

Freedom & Independence: You Pick the Technology, The Library, The Fab

Use the Xtensa processor core in any IC manufacturing technology, from any silicon source - traditional standard-cell ASIC, foundry COT, or programmable logic. The choice is yours.

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PRODUCT RESOURCES
Xtensa 7 Product Brief
Xtensa Processor Developer's Toolkit Product Brief
  Microprocessor Report's Update on Xtensa LX2 and Xtensa 7
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WHITE PAPERS
Configurable Processors: What, Why, How?
Catching Up with Moore’s Law: How to Exploit the Benefits of Nanometer Silicon
ARTICLES
Reducing SOC Simulation and Development Time
How to Improve ROI in SOC Designs
Automated Verification of Configurable IP Blocks
MPEG-4 is Accelerated with Xtensa V
How Tensilica Verifies Processor Cores
QUOTABLE

“We were faced with lengthening RTL (register transfer level) hardware design cycles. By using Xtensa processors, we cut the design time significantly, plus benefit from the programmability of the solution.”

Dr. Jong-Seok Park,
Vice President of LG.

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