Build Processors Tailored to Your Application
Each instance of the Xtensa processor core is
unique to the designer who creates it. Applications
are not locked into a set of features that were
predetermined years or decades earlier by a processor
designer.
Configurability of a Tensilica processor core never compromises the underlying base Xtensa instruction set, thereby ensuring availability of a robust ecosystem of third party application software and development tools. All configurable, extensible Xtensa processors are always compatible with major operating systems, debug probes and ICE solutions; and always come with an automatically generated, complete software development toolchain including an advanced integrated development environment based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry-standard GNU toolchain.
| Configurable |
Select
from thousands of combinations of predefined
processor elements – floating point,
MMU, cache size, DSP engines, interface
widths, register file size. |
| Extensible |
Designer-defined and application-specific
instruction extensions speed the
performance of the Xtensa processor for
the target application by 10X, 100X,
or more – complete with new hardware
execution units, register files, and
processor state variables. |
| Automatically
Supported with Full Software Tool Suite,
Modeling Tools, and RTOS Tools |
All
configuration options and every designer-defined
instruction are automatically supported
by
- Complete software tool suite – compiler,
linker, assembler, profiler
- Operating systems – Mentor
Graphics Nucleus Plus, Express Logic's ThreadX, Micrium's uC/OS-II, Linux, and Sophia Systems' uITRON.
- Modeling & EDA Tools – Instruction
Set Simulator, multiple-processor
XTMP Modeling and System-Simulation
Environment, Co-Verification & Co-Simulation
bus functional models, and optimized
EDA scripts
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The Xtensa Processor Generator Makes It Possible
The system designer or the hardware or software
developer uses the Xtensa Processor Generator
to select the instruction set options, memory hierarchy,
closely-coupled building blocks and external interfaces
required by the application. The Xtensa Processor
Generator runs on a secure server and is accessed
over a secure Web conection. In addition to the
configuration options, a system designer can describe
additional data-types, instructions, and execution
units using the Tensilica Instruction Extension
(TIE) language. The Xtensa Processor Generator
then produces both the complete synthesizable hardware
design and the tailored software environment in
minutes.
The synthesizable RTL hardware description produced
by the Xtensa Processor Generator is ready for immediate
integration with other IP blocks into an SOC design.
You can quickly and easily target the Xtensa processor
to any silicon target technology (ASIC, COT foundry,
FPGA) for the ultimate cost leverage. Software
development, system-level simulation, and application
tuning can also start immediately by using the
profiler, various simulation models and overlays
for supported RTOSes.
Explore Alternative Solutions: Iterate in Hours
The Xtensa Processor Generator assists designers
in creating tailored, application-specific embedded
processors quickly and reliably. With each instance
of the Xtensa processor taking only minutes to create,
designers can explore hardware-software tradeoffs
that were never possible using rigid, fixed-architecture
processors. And designers can explore multiple
architectures by making area, speed, power and
code-density design tradeoffs based on real-time
feedback using the sophisticated estimator built
into the Xtensa processor generator.
Find out How Tensilica Verifies Processor Cores.
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