Performance Leadership
Because it can be matched perfectly to your application,
the Xtensa 7 processor core is much faster than
other 32-bit processors and rivals hand-coded RTL
performance. Particularly
when custom TIE instructions are
added, the performance impact can be outstanding.
See the chart below.
Leading the Industry Benchmarks
The enhancements made to Xtensa 6, in particular
to the XCC compiler, have enabled Tensilica to
extend its lead in overall processor performance
on two industry-standard benchmarks: EEMBC and
Dhrystone.
In the EEMBC benchmark suite – an independently
certified benchmark developed to measure the performance
of processors in a variety of embedded applications – Tensilica
posted the highest scores ever published for a
processor core on the Network, Telecom and
Office Automation tests.
Both “Optimized” and “Out of
the box” configurations of Xtensa were tested. “Out
of the box” tests measured the performance
of cores using unmodified C-code, while “Optimized” tests
measured the performance of Xtensa with modifications
to the C code to utilize the TIE instruction extensions
to optimize performance. No assembly coding was
used in the EEMBC benchmarks, and no assembly coding
is ever required to utilize the power of TIE extensions.
For more information on Tensilica’s EEMBC benchmarks,
see:
Another universal yardstick for measuring processor performance is the Dhrystone
benchmark (v2.1). The Xtensa 32-bit core outperforms processors from
ARM and other companies on this benchmark, delivering 2.0 DMIPS/MHz with
full optimization, and 1.2 DMIPS/MHz with no in-lining. For example, the
ARM 1020E delivers 1.7 and 1.2 DMIPS/Mhz, respectively. All data current
February 2003.
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