The Xtensa
processor’s floating-point
unit (FPU) adds the logic and architectural components
needed for 32-bit IEEE 754 single-precision floating-point
operations. These operations are useful, for
example, for DSP algorithms that require better
than 16 bits of precision, such as high-quality
audio compression and decompression. Also, DSP
algorithms operating on less precise data are
more easily coded using floating-point (because
of the wide dynamic range), and floating-point
operations boost the performance of many programs
written in high-level programming languages such
as C. Optimized for printing, graphics, and audio
applications, the floating-point unit provides
the programming ease of floating point at the
low overhead cost of fixed-point processing.
The Xtensa processor FPU is remarkably small
for such a full-featured FPU. It only consumes
17.4K gates at slow speed and 23.7K gates at
maximum speed. Using flip flops instead of latches
adds about 1.5K gates, making the total gate
count only about 25K gates (including floating-point
registers) for a very efficient, full-featured
implementation.
The floating-point unit is an option for the
Xtensa 7 and Xtensa LX2 processors. The floating-point unit
uses separate integer and floating-point execution units;
this provides high sustained throughput for floating-point
intensive code. Because Xtensa processors are
configurable and extensible, additional optimizations
can be made by the designer. If the floating-point
option is not selected, the compiler emulates
the floating-point operations in software.
Major Features
- 16 dedicated floating-point registers
- Full set
of load/stores, offset and indexed address
update modes
- 34 additional instructions added directly
to hardware
- Fully pipelined arithmetic operations
in hardware:
- add, sub, mul, madd, msub with 4-cycle
latency
- loads and converts with 2-cycle latency
- moves,
compares with 1-cycle latency
- Full compiler support
for C/C++ floating point
- Peak performance 2.0
Mflops/MHz
Double-Precision Floating Point Emulation Acceleration Application Note
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Double-precision floating point is used in applications that require precision greater than single precision floating point. In Tensilica processors, these operations are implemented with a software emulation library. This application note presents a small set of TIE instructions and states that can be used for speeding up the existing double-precision software emulation.
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