A World-Class Processor Core

The Xtensa 32-bit architecture features a compact instruction set optimized for embedded designs. The base architecture has a 32-bit ALU, up to 64 general-purpose physical registers, 6 special-purpose registers and 80 base instructions, including improved 16- and 24-bit (rather than 32-bit) RISC instruction encoding. The Xtensa CPU implements the proven Xtensa instruction set architecture (ISA), which enables designers to achieve significant code size reductions compared to conventional RISC cores. Reducing code size results in higher performance and better power dissipation - key to saving cost in highly integrated SOC designs. The Xtensa ISA's 16- and 24-bit encoding also provides powerful branch instructions and zero-overhead loops, and bit manipulations including funnel shifts and field-extract operations.

Configurability of a Tensilica processor core never compromises the underlying base Xtensa instruction set, thereby ensuring availability of a robust ecosystem of third party application software and development tools. All configurable, extensible Xtensa processors are always compatible with major operating systems, debug probes and ICE solutions; and always come with an automatically generated, complete software development toolchain including an advanced integrated development environment based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry-standard GNU toolchain.

Optional pre-defined execution units:

• 32-bit or 16-bit multiplier
• 16-bit MAC
• Floating-point unit

Configurable interface options:

• 32/64/128-bit processor interface (PIF) width to main system memory or to an on-chip system bus. Tensilica provides a complete Vera-based tool kit for PIF bridge implementation and verification
• "No PIF" configuration option
• Optional high-speed Xtensa Local Memory Interface (XLMI)
• Write buffer: selectable from 4 to 32 entries
• Memory management options and on-chip memory architecture options

Memory Subsystem Options

• Memory management options
• Memory management unit (MMU) with Translation Look Aside Buffers (TLBs), includes No Execute Bit security support
• Local data and instruction caches
• Separate local RAM, ROM areas for data and instructions, up to 256Kbytes each
• Optional parity or ECC for all local memories

Multiple processor design support:

• System modeling capability: optional Xtensa Modeling Protocol (XTMP) simulation environment, which is compatible with SystemC
• Multiple-processor on-chip debug capable with break-in/out control
• Optional processor ID interface and special register
• Memory synchronization and conditional store instruction option provides support for memory semaphore operations and the release consistency model of memory-access ordering

Complete hardware implementation and verification flow support:

• Automatic generation of RTL and tailored EDA scripts for leading-edge process technologies, including physical synthesis and 3D extraction tools
• Auto-insertion of fine-grained clock gating delivers ultra-low power
• Hardware emulation support including automated FPGA netlist implementation
• Comprehensive diagnostic test bench
• Major standard and physical synthesis design flows supported

High-speed, high-accuracy system simulation models automatically created for each configuration:

• Pipeline-modeled, cycle-by-cycle accurate Xtensa instruction set simulator
• Multiple-processor simulation with XTMP option
• Hardware-software co-verification model for Mentor Seamless

Comprehensive development environment and software tool support:

• Xtensa Xplorer development environment accelerates the analysis and development of Xtensa processor cores and SOCs designed with multiple Xtensa processors
• Seventh generation Xtensa Tools development suite automatically configured for each processor, including the advanced Xtensa C/C++ compiler (XCC)
• OS support for Mentor Graphic's Nucleus Plus, Express Logic's ThreadX, open source Linux, Micrium Technologies' uC/OS-II, and Sophia Systems' uITRON

XPRES Compiler support:

• Automated configuration synthesis from C/C++ source code, no code modification required

Performance Summary

Processor architecture:

• High-performance 32-bit RISC with 5-stage pipeline

Instruction set:

• Xtensa ISA with compact 16-bit and 24-bit base instruction set