Xtensa Optimized Results Show Power of TIE

EEMBC allows two scoring methods: “Out-of-the-box” and “Optimized.” “Out-of-the-box” tests measure performance using unmodified C-code, while “Optimized” tests measure performance after modifications, or optimizations, have been made to the C code. The Xtensa core was optimized using the Tensilica Instruction Extension (TIE) language to optimize performance. The TIE language enables designers to develop an unlimited variety of user-defined instructions. No assembly coding was used in the EEMBC benchmarks, and no assembly coding is ever required to utilize the power of TIE extensions.

The EEMBC results show that the base Xtensa processor is 17 to 111 percent faster than the ARM1020E on Out-of-the-box EEMBC benchmarks, while the optimized Xtensa core outperforms the ARM1020E by 7X to 33X (all scores normalized to 1 MHz). In some cases, the Xtensa core outperforms even full-chip, multi-million- transistor standalone processor ICs that are as much as 100 times the size of the Xtensa core, proving the efficiency and integration enabled by the Xtensa architecture and the immense power of designer-defined extensions. Read about the exact configurations used.

Tensilica Xtensa processor: approx. 0.8 - 2.0 mm2 in 0.13um as configured, three separate configurations used, simulated optimized scores.

ARM: Out-of-box scores for ARM1020E architectural core.

Motorola: MPC7455 CPU, 1GHz full-chip device, 483-pin CBGA, 21W power dissipation. Optimized: network and telecom. OOB: consumer.

MIPS 20Kc core, 200 MHz simulated out-of-box scores in 0.13um.

TI:  TMS320C6203, 300MHz full-chip DSP, optimized.

All data updated February 2003. Source: www.eembc.org