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GSPx Paper: “SOC-Based
Signal Processing:
Meeting Performance Goals With Tailored DSPs” (pdf)
Xtensa 7 DSP Options
A Different Way to Look at “DSP”
Digital signal processing – or DSP – tasks
comprise the bulk of the data-intensive computational
requirements for most SOCs in consumer, telecommunications,
and wireless systems applications. Tensilica’s
customers today are already using the Xtensa processor
core for a variety of DSP tasks including audio
processing, image processing, video processing,
and communications channel processing. The Xtensa
7 processor can be used in such a wide variety
of applications because Tensilica offers three separate
means of accelerating DSP computations.
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Moderate
Performance |
Very
High Performance |
| Function
or Application Specific Designer-Defined
Instructions |
Simple
TIE
- Single-Cycle Instructions
- Single Operation per Instruction
- Compiler Support Through Automatic
Intrinsics
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Advanced
TIE
- Multiple-Cycle Instructions
- Multiple Operations per Instruction
- SIMD Operations
- Overlapping of Computation and
Load/Store Operations
- Compiler Support Through Automatic
Intrinsics
|
| General-Purpose
Click-Button Configuration Options |
MAC16
Function Unit Option
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MAC16 Configuration Option
For moderate intensity signal processing applications,
a 16-bit multiply-accumulate engine can be added
to the base Xtensa 6 processor core with just a
click of a configuration button in the Xtensa processor
generator. Inclusion of the MAC16 option adds a
full suite of multiply / accumulate instructions
including auto-incrementing loads and combined
multiply-accumulate-load instructions for high
performance computation. These DSP instructions
are also 100% compiler supported.
Simple Tensilica Instruction Extensions (TIE)
For applications with one or more signal processing
applications that require some amount of acceleration
beyond the base RISC processor features of Xtensa
6, the designer can quickly add instructions and
hardware execution units tailored to a specific
algorithm.
For example: the “butterfly” operation
used in Convolutional Coding / Viterbi Decoding
applications is a series of combination Add-Compare-Select
(ACS) operations. If the data in question consists
of 8-bit values packed in the standard 32-bit registers
of Xtensa, a designer can easily add an ACS instruction
the Xtensa processor with a small incremental block
of execution unit hardware to greatly speed up
Viterbi decoding for communications applications.
Advanced Tensilica Instruction Extensions (TIE)
For applications with well-defined, very high
performance signal processing computational demands,
the TIE language provides a fast means of developing
extremely powerful DSP extensions. Add custom registers
and register files for unique data types. Create
complex multiple-operation instructions and automatically
pipeline those instructions into multi-cycle instructions
by specifying a command directive in the TIE language
that takes only one line of text in a TIE description.
Create SIMD (single instruction, multiple data)
instructions to tackle algorithms with native data
parallelism. Use software-pipelining techniques
to create combined compute-and-load, compute-and-store
instructions for high data-rate applications that
enable continuous computation without the performance
overhead of processor load and store cycles.
For more information on the Xtensa 7 processor
architecture, click here.
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