Build Processors Tailored to Your Application
Each instance of the Xtensa processor core is
unique to the designer who creates it. Applications
are not locked into a set of features that were
predetermined years or decades earlier by a processor
designer.
Configurability of a Tensilica processor core never compromises the underlying base Xtensa instruction set, thereby ensuring availability of a robust ecosystem of third party application software and development tools. All configurable, extensible Xtensa processors are always compatible with major operating systems, debug probes and ICE solutions; and always come with an automatically generated, complete software development toolchain including an advanced integrated development environment based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry-standard GNU toolchain.
| Execution
Unit and ISA Options |
- 16-, 32- or 64-entry register files
- Single-cycle multipliers - 32 or 16-bit
- Low-area multicycle 32x32 multiplier
- Low-area integer divider
- Single 16-bit MAC
- Floating Point Unit – IEEE754
compatible, 32-bit single precision
- Multiple-processor synchronization instruction set option
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| Interface
Options |
- Processor Interface Width: 32/64/128-bit
- Optional "no PIF" configuration
- Inbound DMA option
- Big-Endian/Little-Endian byte
ordering
- On-Chip Debug (IEEE 1149.1 compliant)
- Trace Port
- Xtensa Local Memory Interface
(XLMI), a high-speed local interface
- Up to 32 interrupts, with up to
7 levels of priority plus a separate
Non-Maskable Interrupt level
- AMBA 3 AXI or AMBA 2 AHB-lite bridge
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| Memory
Subsystem Options |
- Memory management options:
- Region protection
- Region protection with translation
- Configurable Memory Management
Unit (MMU) with Translation Look Aside Buffers (TLBs), includes no-execute bit security support for Linux support. NOTE: See Tensilica's open-source Linux website.
- Region protection
- Local Data and Instruction Caches
- Up to 4-way set associative
- Up to 32 KBytes
- Write-back and write-through cache write policy
- Separate RAM and ROM areas for
data and instructions, up to 256Kbytes each
- Independent interface widths for all local memories and system bus
- Optional parity or ECC for all local memories
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| Design
Support |
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| OS
Support |
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