A Better Basic Architecture
The Xtensa Instruction Set Architecture (ISA)
was designed from the ground up for embedded applications. With
advanced architectural features such as a register-windowing
scheme that accelerates function calls, and built-in
zero-overhead loop capability to accelerate the
repetitive inner code loops typically found in
embedded computing applications, the Xtensa processor
delivers superior performance in most embedded
applications on ‘out of the box” application
code.
The Proof
The EEMBC benchmarks prove it. EEMBC results include
two types of performance testing – “out
of the box” and “optimized. As the
name implies, “out of the box” literally
means taking the unadulterated benchmark C code – no
code tuning, no assembly coding, no algorithm restructuring – and
running it through a compiler and measuring the
results.
The following chart compares EEMBC Out-of-the-Box
benchmark performance for several licensable processor
architectures on a per-MHz basis– a true
and fair measure of pure ISA architectural strengths.
EEMBC "out of box" scores: Identical C
source code compiled to target architectures. Xtensa
optimized scores are 4X to 23X faster. Simulated
scores except NEC
This optimized architecture is extremely efficient
because of its very small code size.
Read our Xtensa Architecture White Paper.
|
