Adding Instructions Through TIE - The Tensilica Instruction Extension Language

To add a new instruction to the Xtensa 7 processor core, a designer expresses the desired functionality in the Tensilica Instruction Extension (TIE) language. TIE is a Verilog-like language used to describe desired custom instructions. You can also specify that a complex instruction be implemented as a multi-cycle instruction with a single TIE language directive.

While designers can manually write TIE instructions, Tensilica has an easier alternative. The XPRES Compiler can be used to automatically create TIE instructions. Just input your C/C++ algorithm and the XPRES Compiler will analyze thousands of different Xtensa configurations that will accelerate the algorithm. The designer choosed the best TIE-based configuration (based on power, performance, or area) and the automatically created TIE is ready to be input into the Xtensa Processor Generator.

Adding TIE instructions to a Tensilica processor core never compromises the underlying base Xtensa instruction set, thereby ensuring availability of a robust ecosystem of third party application software and development tools. All configurable, extensible Xtensa processors are always compatible with major operating systems, debug probes and ICE solutions; and always come with an automatically generated, complete software development toolchain including an advanced integrated development environment based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry-standard GNU toolchain.

The TIE language can describe new registers, register files, and custom data types – such as 24-bit data for audio applications, 56-bit data for security processing, 256-bit data types for packet processing – whatever your application requires. Why create odd-sized data types and registers? Matching register sizes to the corresponding data types saves area and power (by eliminating unused bits) Further, a custom-designed register file and special single-cycle instructions can efficiently handle DES encryption algorithms (for example) while a rigid processor core with a fixed instruction set might take 20 or 40 or more cycles.

A designer creates a TIE file defining new functions and data types using the TIE development and analysis tools in Xtensa Xplorer Processor Developers Edition (Xplorer-PDE). The TIE file can be used with the TIE compiler to create updated software tools and instruction set simulator within minutes, on the desktop. Try this with other configurable processors, and you’ll have to integrate new instructions manually over a span of several weeks.

When you want to build the whole core and RTL, turn to the Xtensa Processor Generator.  In minutes, the Xtensa Processor Generator automatically builds a correct-by-construction RTL (register transfer level) description of the Xtensa processor that includes all the newly described functions and resources, as well as a complete software tool suite that incorporates the new TIE instructions, registers, and data types. Because the processor and software development tool suite are generated from one source description and a common database, the software development tools track the processor hardware and there is no possibility of a mismatch. Tensilica is the only company to offer this level of risk-free automation for configurable and extensible processors.

Higher-Level TIE Syntax

Now designers can specify new instructions at a much more abstract level, whicih makes it much easier to experiment with different Xtensa processor configurations using Xtensa Xplorer. The higher-level syntax describes a potential new instruction without first needing to explicitly defining details such as opcode encoding or operand encoding, and without fully specifying the detail of the functional implementation or the details of user-defined register files and state variables. Tensilica’s TIE Compiler can automatically determine the optimal instruction encodings and implementation in minutes using a process that “maps” the abstract instruction definition into a detailed implementation description.

This higher-level TIE syntax has several benefits:

• Faster exploration of custom instruction ideas
• Significantly easier re-use
• Significantly easier to combined “solution packages” from multiple creators,within companies and from third party providers.

For example, the following illustration shows a SIMD vector add instruction

The TIE Compiler “maps” the ADD16x4 instruction to an available Opcode and creates Load/Store instructions for the new 16-entry register file named “vec”. Hardware (RTL) for the instruction and register file, plus simulator, compiler with “vec” type support, assembler, debugger, and RTOS are autoamtically generated by the Xtensa Processor Generator from the TIE description.

Read more about accelerating existing application code.

Read more about designing SOC hardware using task engines based on Xtensa processors instead of HDL-based logic blocks.

Read more about the TIE Compiler.

For an example of how a configurable processor can be extended, see the article MPEG-4 is accelerated and footprint reduced by use of a configurable processor core.

EEMBC Benchmarks - TIE Results in Excellent Optimized Scores

The results are in. Adding TIE instructions provide optimized scores better than any other embedded processor. Check out the results.