388VDO Video Processor

See Microprocessor Forum Presentation: 388VDO Dual Core Video Decoder/Encoder (PDF)

Main Profile Video Encoder and Decoder

The 388VDO Video Engine is customized for multi-standard, multi-resolution video in SOC designs. Targeted at mobile handsets and personal media players (PMPs), the 388VDO supports the following video standards:

Resolutions up to 720x480 (NTSC) and 720x576 (PAL) are supported, as are lower resolutions including QCIF, QVGA, CIF and VGA.

The 388VDO Video DSP includes two customized Tensilica cores for maximum efficiency. See the VDO Processor Architecture page for more details.

The 2-Core 388VDO Video DSP

Tensilica supplies both the hardware (in RTL) and the software codecs for the 388VDO Video DSP. With the optimized video instructions, developers can port their own codecs to the 388VDO Engine entirely in C, saving time compared to assembly language programming.

Tensilica also provides a complete matching software development tool-chain including an advanced integrated development environment based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry standard GNU toolchain. In addition, Tensilica’s wide partner network provides operating systems, debug probes, ICE solutions, and other support needed to help get Tensilica’s processors designed in quickly.

Features

• Video codec processor for consumer entertainment devices
• Fully software programmable in C/C++
• Rich software tool chain
• Supported by a library of most common codecs
• Capable of encode and decode in real time
• Optimized for block-based codecs
• Very low power, low area
• Simulation model with video test streams available for evaluation and software development
• FPGA prototype available or demonstration and evaluation

Benefits

• One engine for all codecs
• Programmable for new or changing standards
• Low power and small area footprint is ideal for portable and mobile applications
• Pre-packaged, ready to drop-in module for easy integration into SOC designs
• Custom video specific instructions for better code density and fewer cycles.

Applications

• Many-format Internet-enabled handsets
• Full-duplex video conferencing
• IPTV set-top box
• DTV receivers employing proprietary error correction and concealment methods in software
• PC low-power video acceleration
• Lossless encoding of traffic monitoring video for law enforcement
• Video-enabled home appliances

Turnkey Video for SOC Designs

The 388VDO Video DSP hosts all the key video processing functions in software on the cores - including the network abstraction layer, slice layer, bit-stream parsing and entropy decoding and encoding.

The Flexibility of Processor-Based Video Decoding

The 388VDO DSP core compares quite favorably to the traditional approach of using pure hardware based video accelerators in tandem with conventional CPUs. First, the 388VDO offloads the full video decode task – including all bit-stream parsing – from the system host CPU. Conventional hardware accelerators only offload the pixel processing functions like motion estimation, and leave a large compute burden on the system controller.

Second, conventional solutions consisting of a CPU plus a hardware accelerator burn a huge amount of wasted power in the system bus when shuffling data to and from the CPU and accelerator – power that is often conveniently not counted by other IP vendors that boast that their HW accelerator block itself burns only a small amount of power.

Third, when the 388VDO DSPis not being used to perform video tasks, it is a ready resource of over 500 Dhrystone MIPS of general-purpose CPU power available to perform other system tasks – whereas a dedicated video HW block can never be reused.

Fourth, the 388VDO DSP is programmable and, therefore, can host future video standards that emerge in the coming years.

Low Area, Low Power

The 388VDO DSP is optimized for mobile applications and requires a smaller area and consumes less power than competing solutions. Through the use of fine grained clock gating, a feature of the Xtensa processor architecture, and the integration of power management instructions which provide programmability to throttle power under varying video work loads, active power is further minimized. Additional power efficiency is achieved through the implementation of the DMA engine and interface to the Stream and Pixel Processors that minimizes the external memory bandwidth requirements.

In area efficiency for example, the full-featured 388VDO delivers Main profile H.264 support for decode and MPEG-4 ASP encode at D1 resolution yet consumes only 11.2 mm², including memories, and runs at 200 MHz in TSMC 0.13G process technology. With TSMC 90G technology at 300 MHz, the 388VDO consumes only 6.6 mm², including memories.

Even when running codecs, the 388VDO consumes very little power. For example, it can do H.264 Main and Baseline Profile decode at D1 resolution with a bit rate of 5 Mbps and processor power of 47 mW, including all processor power sinks: logic, SRMA, clock tree, and leakage, as measured with Synopsys Power Compiler on a TSMC 90G layout netlist generated with Virage standard cell and SRAM libraries for a simulation of decoding the Akiyo sequence with 32 cycles main memory access latency.

Easy Hardware Integration

It's easy to integrate the 388VDO into your SOC design.

No GPL Obligations

All codec software is available from Tensilica and free of GNU Public License obligations. Your designs and your customers' designs incorporating Tensilica codec software need not be publicly licensed. You may charge money to all of your customers for your software incorporating Tensilica codec software. And products incorporating Tensilica codec software may implement DRM.

An Advanced Architecture Optimized for Video

Please click here for more information on the architecture behind the 388VDO processor.

Performance Summary