An optional full-speed, non-intrusive instruction trace capability has been added for all Xtensa configurable processor cores. Tensilica’s TRAX-PC processor trace capture macrocell is Nexus 5001 compatible and ideal for debugging complex, challenging real-time applications such as engine and motor control. Software control and use of the on-chip TRAX hardware is fully integrated into Tensilica’s Xplorer integrated design environment (IDE) so software engineers can easily develop and debug programs while using the TRAX-PC trace macrocell.

Difficult debugging problems are sometimes caused by subtle interactions between subsystems and other timing consideration in hard real-time systems. State-of-the-art processor trace tools can ease system integration, solidify product schedules and accelerate revenues. By adding trace capability, designers can feel confident in their ability to debug and deploy FPGA prototypes or SOC silicon solutions.

Tensilica’s TRAX-PC processor trace capture block provides tracing information through an SOC’s JTAG debug port without requiring added device pins. It helps designers trace all changes in program flow including exceptions and interrupts. The trace block uses a circular on-chip trace buffer with user-defined sizing to capture the trace stream and accepts PC-based triggers and external trigger inputs.

Tensilica’s associated software tools convert the compressed trace into an annotated program disassembly for easy debugging. These tools are fully integrated into Tensilica’s world-class Eclipse-based, Xtensa Xplorer integrated design environment (IDE). The Xplorer IDE provides a powerful visualization and debugging environment to both develop and debug programs using the TRAX-PC trace macrocell.

The user can set a stop trigger via PC address or address range, manually stop execution by executing stop trigger, or set the amount of trade to capture after a stop trigger. The trace compressor hardware has two external inputs and outputs, enabling cross triggering between processors and other RTL blocks.

Tensilica is a member of the Nexus 5001 forum, a program of the IEEE/ISTO. The Nexus 5001 interface offers non-intrusive real-time visibility and control of single- or multi-core embedded systems. It is an open industry standard that provides real-time trace, CPU control, real-time data monitoring, and system-level debugging of single-core or multicore systems. It supports breakpoint debugging and flash programming, as well as rapid prototyping, calibration, and JTAG boundary-scan testing. The standard is freely downloadable from the Nexus 5001 website (http://www.nexus5001.org), and is enhanced and maintained by an expanding list of member companies.