A Modern, Efficient Architecture

All of Tensilica’s processors are based on the proven Xtensa architecture, which is used across a wide range of electronic products, from low-cost portable consumer applications to carrier-class networking routers. Whether used as an efficient programmable controller or as an audio processor, high-performance DSP or high-speed processor, the Xtensa Instruction Set Architecture (ISA) is the ideal architecture for almost any application in any market.

How can one architecture the "the best" for so many different markets? Because Tensilica essentially gives you the equivalent of a $15 million architectural license to modify its processors, plus patented, automated tools that assure that your modifications will be made properly.

On top of that, Tensilica's tools automatically generate a complete, matching tool chain for any configuration or set of extensions. So you always have the software support you need that exactly matches your own processor.

This lets you build in your own differentiation into your products. Your products will be harder for competitors to copy, since you're using your unique processor instead of an industry standard core that anyone can purchase.

Of course, if all you need is a simple controller or DSP, we offer our Diamond Standard product line of Tensilica-optimized cores, built on the same foundation. Essentially, we picked the configuration options and/or extended the processor ourselves so you don't have to.

A Superior Instruction Set Architecture

The Xtensa Instruction Set Architecture (ISA) is a 32-bit RISC architecture featuring a compact instruction set optimized for embedded designs. The architecture has: a 32-bit ALU; 16, 32 or 64 general-purpose physical registers; six special purpose registers; and 80 base instructions. The Xtensa ISA employs 24-bit instructions with 16-bit narrow encodings for the most common instructions. These 16-and 24-bit instruction words are freely intermixed to achieve higher code density without compromising application performance. On some processors, 64-bit VLIW encoding is utilized when efficient, and these 2- or 3-issue instructions are also modelessly intermixed with 16- and 24-bit instructions. The Xtensa ISA thus optimizes the size of the program instructions by minimizing both the static number of instructions (the instructions that constitute the application program) and the average number of bits per instruction.

The use of 24- and 16-bit instruction words, the use of compound instructions, the richness of the comparison and bit-testing instructions, zero-overhead-loop instructions, register windowing, and the use of encoded immediate values all contribute to the Diamond processors’ small code size. Thus, the 24-/16-bit Diamond processor ISA enables designers to achieve 25% to 50% lower code size compared to conventional 32-/16-bit ISA-based RISC cores. Reducing code size results in smaller memory sizes and lower power dissipation – key parameters in cost-sensitive, highly integrated SOC designs.

Tensilica's Xtensa architecture is much more efficient and results in smaller code size than ARM and MIPS.
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Create an Optimized Processor in Minutes

By selecting and configuration predefined elements of the architecture and by inventing completely new instructions and hardware execution units, Xtensa processors can deliver performance levels orders of magnitude faster than standard 32-bit processor cores. Designers define new instructions utilizing the Tensilica Instruction Extension (TIE) methodology, adding Verilog-like descriptions of datapaths, execution units, and register files that can deliver performance, area, and power characteristics equivalent to custom logic design.

Or, the designer can use the XPRES Compiler to analyze the C/C++ algorithm and automatically suggest configuration options and extensions that will run that algorithm faster. Compared to traditional hardware design, Xtensa processors deliver similar quality of results with the added benefits of accelerated design time and post-silicon software programmability, making Xtensa 7 processors ideal choices for all complex SOC designs.

Profile the application software, configure the Xtensa core and add new instructions to optimize performance - all in a matter of minutes in Tensilica's Xtensa Xplorer design environment. Before committing to silicon, system designers can explore multiple architectures by making area, speed, power and code-density design tradeoffs based on real-time feedback from the Xtensa Xplorer environment. Then, the Xtensa Processor Generator automatically creates tailored, application-specific embedded processors quickly and reliably, to your exact specifications. Pre-verified, correct-by-construction RTL generation lowers verification efforts.

See how this can work for you in our short Xtensa tour.