Industry’s Only Development Environment
for Multiple-Processor SOC Hardware and Software
Design
Xtensa Xplorer is the only SOC design environment that integrates software development, processor optimization and multiple-processor system-on-chip (SOC) architecture tools into one common platform. You can access powerful design automation tools that ease the creation of Xtensa processor-based SOC hardware and software.
The Xtensa Xplorer IDE serves as the cockpit for the entire design process and provides all the tools necessary for processor and TIE development, software development, and modeling and simulation.
Tensilica’s Xtensa Xplorer GUI serves as the cockpit for the entire design
experience. From Xtensa Xplorer, you can profile your application code, identify “hot spots” that can benefit from acceleration, and make the changes necessary to speed up that code. Using a check-box menu within the GUI, you can configure processors to include features you need and remove features you don’t – options for processor interface, memories, operating system support, EDA scripts, debug and trace, and much more.
From Xtensa Xplorer, you can create, edit and manage Xtensa processor configurations.
You can quickly extend the processor’s instruction set by adding new instructions using the Tensilica Instruction Extension (TIE) language, a hybrid of C and Verilog, which is the easiest-to-use method for saving power, increasing performance, and reducing clock frequency. By modifying the Xtensa processor, Tensilica’s customers often get 10 to 100 times (or more) better performance and lower power when compared to alternative processor architectures.
Xtensa Xplorer includes valuable tools, such as the gate count estimate, to help designers pick the best TIE instructions for their designs.
This allows Xtensa processors to be used in critical SOC functions where previously standard microprocessors or DSPs could not deliver the needed performance, throughput or low-power; and hand-coded RTL hardware blocks had to be used. And this allows Xtensa processors to be used by designers with no previous processor design experience.
Profiling Tools
Application code profiling is an extremely important tool while optimizing the performance of your application code. The Xtensa Xplorer IDE enables designers to graphically view profiling results generated by Tensilica’s pipeline-accurate ISS or by the fast functional simulator, TurboXim. Additionally, for much faster and more accurate profiling, designers can generate profiling data from hardware instantiated in an FPGA or ASIC. Designers can track performance data such instruction execution count, subroutine calls, subroutine total cycles, cache performance, branch delays, interlock cycles, and so on. Note that performance/cycle time profiling information is only available when profiling on real hardware.
While viewing functions in the profiling view, designers can also simultaneously view the assembly code in the disassembly view and the source code in the editor, both of which are annotated with the cycle count of the number of times each line of code is executed. The call graph view enables designers to view the entire application hierarchy caller and callee functions with a cycle count of the function and its callee functions.
There is also a pipeline view that displays a graphical representation of the instructions in a function as they progress through the processor pipeline. This representation is based on a dynamic trace information gathered when the application is executed on the cycle-accurate ISS. The pipeline viewer thus helps designers understand instruction stalls and latency issues.
Designers can profile and visualize the performance impact of base Xtensa and TIE instructions. The designer need not be a “processor expert” to visualize, fine-tune custom instructions for maximum results.
Performance charts visually compare different configurations.
You can profile, compare and save many different processor configurations, so you can pick the right one for your application. Also, you can model and simulate multiple processor subsystems in this environment using Tensilica’s XTensa Modeling Protocol (XTMP) and XTensa SystemC (XTSC) modeling environment.
TIE Compiler and XPRES Compiler
Tensilica’s TIE Compiler automatically creates updates to the entire Xtensa toolchain including the ISS and SystemC models, in minutes on your desktop. From Xtensa Xplorer, you can invoke Tensilica’s XPRES Compiler, which analyzes C/C++ application code and automatically creates TIE code for Tensilica’s Xtensa processors that will significantly speed up that application. This often gives you the performance boost you need without the need to figure out the necessary processor extensions yourself.
Tensilica’s processor configuration tools (Xtensa Processor Generator, TIE Compiler, and XPRES Compiler) can be invoked from the Xtensa Xplorer design environment. In addition, Tensilica’s software development tools (C/C++ toolchain, project management, and performance analysis) are also integrated into the Xtensa Xplorer design environment.
Xtensa Xplorer even includes automated graphing tools that create spreadsheet-style comparison charts of performance. Xtensa Xplorer is particularly useful for the development of TIE instructions that maximize performance for a particular application. Different Xtensa processor configurations and TIE files can be saved, profiled against the target C/C++ software, and compared.
Visualize and Analyze: Rapid Iteration of Complex
SOC Architectures
Xtensa Xplorer not only provides the tools to quickly develop optimized processors and simulate systems of processors, but also provides the tools that enable you to visualize and analyze simulation results, tune system or processor configurations, and rapidly compare alternative implementations.
Project Management and Source Code Editing in Xtensa Xplorer
The Xtensa Xplorer IDE builds on the Eclipse project management and revision control mechanisms. The Xplorer IDE automatically creates and manages project and library builds and makefiles. The designer can set the various tool options and flags (example: compiler, assembler and linker flags) using the build properties dialog window. Multiple build properties can be set depending on whether the target is to build a debug version or optimized version of the application binary. Optionally, designers can create unmanaged projects that allow total designer control over build target properties.
The C/C++ source code editor allows designers to efficiently create and modify their code using rich editing and indexing capabilities. The editor uses syntax highlighting of language features such as keywords, comments, declarations, and strings to enable rapid software development and debugging. Symbol indexing allows program navigation including find declaration, find definition, and find type. Other features in the editor that speed up coding include code completion, auto indenting, and quick diff. Block comment/uncomment is useful when debugging or profiling large source files. Designers can choose other views, such as source outline, make target, and problems.
The rest of the software development tool chain (linker, assembler, debugger) is based on standard GNU tools. Since these tools and the XCC compiler front-end use the same preprocessor as in the GNU tools, the flags for the C/C++ preprocessor remain the same. The assembler and linker also utilize the same flags as the GNU versions of the tools.
Xtensa Debugger
The debugger allows you to target the pipeline/cycle accurate ISS, Tensilica’s TurboXim fast functional simulator, or an external probe to a hardware development board. The GUI-based debugger allows full system visibility into your project; it controls program execution (i.e., C instruction and assembly instruction stepping, stepping into or over functions) and provides views to variables, breakpoints, memory, registers, etc,. The debugger also displays registers and internal wires defined by the designer in TIE instructions. Source and assembly code can be made visible simultaneously while debugging an application and either code window can be single stepped. The debugger interoperates seamlessly with the other development tools (compiler tool chain, instruction set simulator) to allow rapid code development for Xtensa processor systems.
Gateway to Xtensa Processor Generator
Xtensa Xplorer serves as the gateway to the Xtensa Processor Generator. Once a processor configuration is finalized, the Xtensa Processor Generator creates the automatically verified Xtensa processor to match all of the configuration options and extensions you have defined, in less than an hour. A software tool chain is also created matching all processor modifications you have made.
Accelerate SOC Development
Xtensa Xplorer accelerates the development, analysis and optimization of configurable processor cores and processor-based SOCs. Xplorer serves as both an analysis platform for the design of processor-based SOCs and as a front-end development tool to the Xtensa Processor Generator.
Xplorer, while extremely useful for designs with
only one Xtensa processor, is ideally targeted
to multiple-processor SOC (MPSOC) designs. It facilitates
MPSOC development with tools for build management;
profiling; batch building; system memory map assignment;
and integrated multiple-processor simulation, creation,
and debugging using Tensilica’s Xtensa
Modeling Protocol (XTMP).
ECLIPSE Platform
The Xtensa Xplorer IDE is based in part on the
open-source ECLIPSE platform for tool integration.
More information on the ECLIPSE partnership can
be found at www.eclipse.org.
With Xtensa Xplorer, you can
Plus, Xtensa Xplorer provides chip-level design
tools for multiple-core SOCs
See also
TIE language enhancements.
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