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  + For Processor
     Designers

    – Xplorer IDE

    – TIE Compiler

    – Create TIE

    – Develop Configs

    – Analyze Configs

    – XPRES Compiler

    – ISS & TurboXim

    – System Modeling

    – Chip Tools

  + For Software
     Developers

    – Xplorer IDE

    – XCC Compiler

    – ISS & TurboXim

    – System Modeling

    – Real-time Trace

  + IDE & RTOS Support

  + HW Emulation

  Literature & Doc

Analyze Configurations

Xtensa Xplorer - a Total Analysis Environment

Xtensa Xplorer helps designers analyze and select configurations to meet speed/area goals. The Xtensa Xplorer design environment provides automatic estimates of the area impact of designer-defined instructions.

Xtensa Xplorer provides valuable estimates so you can make trade-offs in your designs

Performance charts visually compare different configurations. In the chart below, two configurations are compared and the difference in the number of cycles and the number of cache misses is significant.

The Cache Xplorer automatically profiles code and visualizes results across a range of cache configuration options. The chart below clearly shows the performance impact of varying cache sizes.

 

PRODUCT RESOURCES
Xtensa Processor Developer's Product Brief
Xtensa Software Developer's Product Brief
Flash demonstration of Xtensa Xplorer
WHITE PAPERS
Automated Configurable Processor Design Flow
How to Quickly Simulate Entire SOCs to Explore and Optimize Architectural Performance
ARTICLES
Eclipse Platform Eases SOC Development
Automated Verification of  Configurable IP Blocks
How Tensilica Verifies Processor Cores
Optimizing C Programs for Embedded SOC Applications
QUOTABLE

“In the technology race, however, Tensilica’s start-to-finish processor-development system sets the company apart from the pack.”

Tom R. Halfhill,
Senior Analyst, Microprocessor Report

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