Tech Support | Generator Login | Careers | Contact Us
PRODUCTS

 Overview

 Technology

 Xtensa Customizable

 Audio

 Video

 DSPs

 Diamond Controllers

 HW/SW Dev Tools

   For Processor
   Designers

     Xplorer IDE

     TIE Compiler

     Create TIE

     Develop Configs

     Analyze Configs

     XPRES Compiler

          Optimizations

          Quality of Results

          FAQ

     ISS & TurboXim

     System Modeling

     Multicore Integration

   For Software
   Developers

   IDE & RTOS Support

   HW Emulation

 Literature and Docs

XPRES Compiler Quality of Results

Get the Speed You Need

Tensilica’s XPRES Compiler automatically analyzes your C/C++ code - no changes required - and figures out how to optimize the Xtensa LX processor to run at the speed you need.

The XPRES Compiler works with Tensilica’s Xtensa C/C++ Compiler (XCC) to analyze the performance-critical regions of your application software or algorithm specification. The XPRES Compiler rapidly explores millions of possible processor configurations using a variety of acceleration techniques. The XPRES Compiler then uses this analysis to generate one or more configurations that increase the performance of your code. These configurations consist of TIE (Tensilica Instruction Extension) code that becomes input to the Xtensa LX Processor Generator. The generated TIE files represent a range of customized Xtensa LX processors that trade off increased application performance versus increased hardware (area) cost.

The implications of this are far reaching. Looks at configuration number 8, above. Only 301 gates needed to be added to the base Xtensa LX processor to achieve a 1.5x speedup. That’s like going from 300 MHz to 450 MHz, just by adding 301 gates to the processor. Maybe that’s not fast enough and you need a 10x increase in speed. No other processor could do the equivalent acceleration to give you 3000 MHz! No other processor can be modified the way Xtensa LX can be modified to get the speed you need for very demanding applications.

The XPRES Compiler is fast. For small algorithmic kernels, the XPRES Compiler performs explorations of potential configurations in just minutes. For very large configurations, such as full video codecs, the XPRES Compiler can explore millions of potential combinations of processor configurations in less than an hour. This very rapid exploration allows the system designer to quickly and exhaustively explore a variety of both automatically generated as well as manually generated TIE techniques.

  Dramatic Productivity Enhancement
Application Speedup Configurations Visited Run Time to Generate Configurations
Radix-4 FFT 10.5x 175,796 3 minutes
GSM Encoder 3.9x 576,722 15 minutes
MPEG-4 Encoder 3.0x 1,830,736 30 minutes

How good are these results? You can test it for yourself. Simulate the processor before you build your chip. Run your original C/C++ code. You’ll be amazed that you can get RTL-like speeds with the benefits of a fully programmable processor.

PRODUCT RESOURCES
Xtensa Processor Developer's Toolkit Product Brief
Demo of XPRES Compiler
WHITE PAPERS
XPRES Compiler: Triple-Threat Solution to Code Performance Challenges
Automated Configurable Processor Design Flow
XPRES White Paper: Rapid SOC Development using Automatically Generated Processors
ARTICLES
Tensilica’s Automaton Arrives by Microprocessor Report
Compiler Leverages Automation Power of CPU Core
Tensilica Compiler Automates RTL Generation
QUOTABLE

“It’s not just that XPRES can automatically generate custom hardware from C/C++ code…. Rather, it’s the whole tool chain and design flow that sets Tensilica’s technology apart. Tensilica is closer than any other company to realizing a vision of software-driven automated hardware design that for decades has mesmerized engineers, academic researchers, and entrepreneurs.”

Tom R. Halfhill,
Senior Analyst, Microprocessor Report

get more info