A High-Performance Processor

• Highly efficient, small, low-power base 32-bit modern architecture
• Configurable over a wide range of options – get just what you need
• Configure processor as a multi-issue VLIW using FLIX architecture
• Extend processor with application-specific instructions, execution units, and register files
• Unlimited I/O bandwidth with designer-defined FIFO, GPIO, and Lookup interfaces
• Automated fine-grained clock gating for ultra-low power
• Designer-selectable 5-stage or 7-stage pipeline depth
• Automatic synthesis of processor configurations and extensions with XPRES Compiler
• Local memories configurable up to 4MB with the option for parity or ECC
• Modelessly intermix 24-bit base ISA instructions with 16-bit narrow instructions and VLIW instructions

Benefits

• Implement hardware architecture equivalent to RTL-based hardware design, with dramatically faster design time and much lower verification effort
• High bandwidth data flow through processor with flexible I/O interfaces that bypass the system bus
• Quickly and easily scale hardware architecture by simply using more task-customized processors
• Lower verification effort with pre-verified, correct-by-construction RTL generation
• Post-silicon programmability
• Higher code density due to 24-bit ISA leads to savings in memory area

The Xtensa LX2 processor is unlike other processors. Designed from the start to be configurable and extensible, Tensilica's hardware and software development tools let the designer mold the processor to exactly fit the application.

Designers can use the XPRES Compiler to automatically analyze their C/C++ code and generate the processor extensions that will allow that code to run very fast on an Xtensa LX2 processor. Tensilica’s processor generator technology creates a complete RTL hardware description of a customized Xtensa LX2 processor, plus a comprehensive suite of software development tools, EDA implementation scripts, and system models – all in about 1 hour.

• Optional pre-defined execution units
• 32-bit multiplier
• 16-bit MAC
• 4-way SIMD Vectra LX DSP engine
• HiFi 2 Audio Engine
• Floating point unit
• Configurable interface options using simple click-box menus
• Designer-defined I/O Ports with up to 1 million wires
• Optional processor interface (PIF) to system bus, choice of: 32 / 64 or 128-bit width with in-bound DMA [slave mode] option
• Optional high-speed Xtensa Local Memory Interface (XLMI)
• Write buffer: selectable from 4 to 32 entries
• Optional second data load/store unit
• Sea of processors / multiple-processor design style support System modeling capability: optional Xtensa Modeling Protocol (XTMP) simulation environment
• Multiple-processor on-chip debug capable with break-in/out control
• Optional processor ID interface and special register
• Memory synchronization and conditional store instruction option provides support for memory semaphore operations and the release consistency model of memory-access ordering
• Local memory parity or ECC support
• Complete hardware implementation and verification flow support
• Automatic generation of RTL and tailored EDA scripts for leading edge process technologies, including physical synthesis and 3D extraction tools
• Auto-insertion of fine-grained clock gating delivers ultra-low power
• Hardware emulation support including automated FPGA netlist implementation
• Comprehensive diagnostic test bench
• Formal verification support for designer-defined functionality
• High-speed, high-accuracy system simulation models automatically created for each configuration
• Pipeline-modeling, cycle-by-cycle accurate Xtensa LX instruction set simulator
• High-speed (40x-80x) instruction-accurate simulator for software development
• Multiple-processor simulation with XTMP option
• XTensa SystemC (XTSC) transaction-level modeling (TLM) support
• Hardware-software co-verification model for Mentor Seamless
• Comprehensive development environment and software tool support
• Xtensa Xplorer development environment accelerates the analysis and development of Xtensa LX processor cores and SOCs designed with multiple Xtensa LX processors
• Xtensa Tools development suite automatically configured for each processor, including the advanced Xtensa C/C++ compiler (XCC)
• Automatic support of multiple operating systems.