BASIC INFORMATION

• Configurable Processors: What, Why, How? - What is a configurable processor? What can configurable processors do? Why would anyone want to use this type of processor? How can a configurable processor replace RTL coding? How does an engineer design with configurable processors?
• Catching Up with Moore’s Law: How to Fully Exploit the Benefits of Nanometer Silicon - The growth in available transistors creates a design challenge. By increasing programmability, designers can lower design cost and improve design flexibility.
• Xtensa Architecture White Paper (PDF) - Find out more about the Xtensa architecture and why it's superior to older general-purpose 32-bit processor architectures.
• Why High MHz Does Not Mean High Performance - Traditionally, performance has been associated with higher frequency. However, higher performance can be achieved even while running the processor at lower frequency. This leads to not only lower power, but also to better architecture-performance efficiency and lower area. This lower area in turn leads to even more power savings when compared to traditional deep-pipeline RISC processors.

DIAMOND STANDARD PROCESSOR CORES

• Diamond Standard Series Architecture White Paper (PDF) - Outlines the goals, philosophy and innovations inherent in the Xtensa instruction set, used in the Diamond Standard processors. Also provides a description of each processor in the family.
• Diamond Standard Series Software Tool Chain - Demos on Demand - See our tools in action on your computer screen.
• Xtensa Architecture White Paper (PDF) - Find out more about the architecture behind the Diamond Standard cores.

XPRES C-to-RTL COMPILER

• XPRES Compiler: Triple-Threat Solution to Code Performance Challenges - Real-life examples of what the XPRES Compiler can do for bit manipulation, H.264 video blockling filter, SAD algorithm for video motion estimation, and MPEG-4 video decoder.
• Automated Configurable Processor Design Flow (PDF) - Describes Tensilica's fully automated, patented design flow that guarantees that all changes made to the processor are reflected in the software and are correct-by-construction.
• XPRES White Paper: Rapid SOC Development using Automatically Generated Processors - This white paper explains the major decisions in architecting an SOC and guides the designer to a systematic approach to design structure using processors as the fundamental building blocks of the SOC.
• XPRES Compiler - Demos on Demand - See XPRES Compiler in action on your computer screen

XTENSA LX2

• Xenergy Energy Estimator White Paper - The Xenergy tool is the first tool that provides a realistic way to estimate the overall energy impact of different processor configurations and extensions. It also helps software developers with energy-driven application code tuning on the overall processor plus memory subsystem.
• FLIX: Fast Relief for Performance-Hungry Embedded Applications (PDF) - Flexible Length Instruction eXtensions give processors an impressive performance boost.
• Increasing Computational Performance Through FLIX (Flexible Length Instruction Extensions) - By packing multiple operations into a wide 32- or 64-bit instruction word, FLIX technology allows designers to accelerate a broader class of “hot spots” in embedded applications while eliminating the performance and code-size drawbacks of VLIW processor architectures.
• How to Optimize SOC Performance Through Memory Tuning - Once the basic organization of instruction, data, and cache memory has been established, detailed memory-system tuning can ensue and make a major difference in performance.
• Queue- and Wire-based Input and Output Ports Allow Processors to Achieve RTL-Like I/O Speeds on SOCs - Wire-based interfaces are familiar to many RTL designers and allow Tensilica's processors to substitute for hardware blocks without even changing the block-interface (“pin”) definitions of existing RTL blocks.
• Think Outside the Bus: High-Speed I/O Alternatives for Inter-Processor Communications on SOCs - This white paper provides short descriptions of the most common hardware mechanisms—buses, direct connections, and data queues—used to interconnect processor cores on SOCs.
• A Quick Guide to High-Speed I/O for SOC Function Blocks - TIE ports and queues allow designers to add many new input and output ports that lead directly into and out of the processor’s execution unit.
• Xtensa LX - Demos on Demand - See a demo showing configuring and adding TIE instruction to an Xtensa LX processor.
• Epson Success Story - Epson realized early on that they could implement nearly any hardware architecture they could implement using hardwired RTL by using Tensilica’s processor extension capability and Xtensa processors. This explains how they did it with multiple Xtensa processors using Ports (GPIOs) and Queues (FIFOs).

LOW POWER

• Processor Core Power Specs: A Cautionary Tale - It's what they don't tell you about power specs that matter.
• Xenergy Energy Estimator White Paper - The Xenergy tool is the first tool that provides a realistic way to estimate the overall energy impact of different processor configurations and extensions. It also helps software developers with energy-driven application code tuning on the overall processor plus memory subsystem.
• Optimizing Energy in Processor-Memory Subsystems during SOC Design - The ability of the Xenergy tool to model designer-defined TIE instruction extensions is critical to designers that use the Xtensa processor as an RTL alternative while designing the data plane of their SOC. Being able to get an early estimate of the impact on energy of their custom TIE instructions is as important to most designers as the area estimation and performance profiling tools.

DSP

• Tensilica Xtensa LX Processor with Vectra LX By BDTI - this BDTI report evaluates the highest performance DSP core BDTI has tested.
• Building a Multi-Issue DSP with Configurable Processor Technology - General-purpose DSPs are not power-efficient for every application due to their general nature. Configurable-processor technology bridges the gap between a DSP’s fixed-ISA flexibility and programmability and hard-wired power efficiency by enabling the creation of full-featured, programmable DSPs that have precisely the right features for a specific task. Tensilica’s Vectra LX—a fixed-point, vector DSP engine created as a configuration option for the Xtensa LX configurable processor—illustrates this concept.
  

SOC DESIGN

• How to Quickly Simulate Entire SOCs to Explore and Optimize Architectural Performance - An effective system-design methodology for complex SOC designs must allow designers to more easily, quickly, and cheaply pull various subsystems together into a whole design and to reliably verify that the assembly is correct.

ESL DESIGN

• ESL Requirements for Configurable Processor-based Embedded System Design - This article explains what it takes to do design at the ESL.

AUDIO/VIDEO

• Low-Power, Low-Overhead, High-Fidelity Digital Sound for SOCs: Tensilica’s HiFi 2 Audio Engine - describes how the HiFi 2 Audio Engine was carefully crafted for the broadest possible range of consumer products.
• Adding Video to SOCs: The Diamond 388VDO Video Engine - Design teams need ways to quickly add proven, tested video functionis to their designs. Tensilica's Diamond 388VDO Video Engine provides such a capacity.
• Flexible VDSL2 Datapath IP for SOC Designs Provides Ready Access to the VDSL2 chip market - white paper from partner UpZide.
• Developing a High-Performance, Programmable MPEG-4 Decoder by Adding a Programmable SIMD Engine to a Configurable, Extensible Microprocessor - Desired video-decoding performance can be achieved by extending a configurable, extensible processor core’s instructions with SIMD (single-instruction, multiple-data) instructions. The publicly available MoMuSys MPEG-4 video decoder (available at www.osi.org) is used as a reference and the TIE language to add the SIMD instructions needed to boost an MPEG-4 simple profile decoder performance.

APPLICATIONS

• Designing Image Processing Pipelines for Printer SOCs using Xtensa Configurable Processors - Configurable processors, such as Tensilica's Xtensa processors, have been used extensively by manufacturers of consumer inkjet and laser printers. Three out of four of the major printer manufacturers have printer SOCs that have Xtensa processors in them. Xtensa processors enable architects to design DSP engines that are customized to particular tasks.