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Diamond Video Engine Controller Code Example --A tutorial on developing control code for the 388VDO Engine

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This application note describes how to write basic control code to control video decoding functionality using the 388VDO Diamond Video Engine.
This tutorial supplements the "Diamond 388VDO Software Guide" by providing a thorough explanation of how the API is used to set up and control theDiamond Video Engine to perform basic video decoding.

Double-Precision Floating Point Emulation Acceleration Application Note

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Double-precision floating point is used in applications that require precision greater than single precision floating point. In Tensilica processors, these operations are implemented with a software emulation library. This application note presents a small set of TIE instructions and states that can be used for speeding up the existing double-precision software emulation.

Emulation Flow for Xtensa Cores

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This application note explains how to map an Xtensa or Diamond core to an FPGA with a minimal on-chip system. This application note includes a demonstration example of an FPGA flow based upon Xilinx logic using RTL for the 108Mini Diamond core.

Audio Reference Design Guide Addendum: System Software Example

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This application note describes a system software example that performs back-to-back audio stream decoding across a variety of audio formats. This addendum is intended to teach a basic approach to developing audio application code for the Audio Reference Design.

Extending the JTAG.v Module

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The jtag.v module provided with Tensilica’s Xtensa LX, Xtensa LX2, and Diamond configurations that include the On-Chip Debug option, is intended as a simple driver model for JTAG TAP. This application note explores a couple of possible extensions to this module: Adding support for new core instructions and modifying the jtag.v module to support multiple Xtensa cores.

Optimizing for Energy using the Xenergy Energy Optimizator Tool

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The Xenergy energy estimation tool enables system architects, software
developers, and TIE instruction designers to evaluate the power and energy dissipation characteristics of design choices and application code early in the development cycle for Xtensa and Diamond processors.

Fast OFDM on Xtensa Processors

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This application note looks briefly at fast signal processing for wireless
modems. In particular, this application note describes the TIE (Tensilica
Instruction Extension) language instructions that accelerate the complex FFT and FIR operations that dominate many OFDM channel modulation and demodulation systems.

Implementing A Mutex and Barrier Synchronization Library on Xtensa

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This application note describes how multiprocessor synchronization instructions can be used to implement a memory-based mutual exclusion (mutex) primitive. This enables tasks running on the different processors to synchronize with each other and safely access shared data. Included with this application note is the complete source code for a C/C++ library that implements an example mutex API as well as a barrier synchronization API.

Implementing FIFO Operations Using TIE Queues

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This application note provides TIE and C code that demonstrate how to implement standard FIFO (First In, First Out) operations using TIE queues. The FIFO operations described in this document include testing for a full or empty FIFO, pushing a value onto a FIFO, and popping a value from a FIFO. This application note also shows how to describe the C data type of the values carried by a FIFO to ensure correct and efficient code generation by the Xtensa C/C++ compiler. The application note and included sample TIE and C code serve as examples for users implementing TIE queues in their designs.

Convolutional Encoding and Decoding, Especially Viterbi Decoding, on Xtensa Processors

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This application note looks briefly at popular techniques for convolutional encoding and decoding, especially Viterbi decoding, and illustrates the power of a configurable processor in handling the performance-intensive signal processing demands of coding and decoding.

Implementing the Advanced Encryption Standard (AES) on Xtensa Processors

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This application note examines the Advanced Encryption Standard (AES) cipher and illustrates the power of a configurable processor in accelerating encryption and decryption. Xtensa-based application-specific processors are quickly designed, simulated, and instantiated in silicon. These processors offer performance that rivals hardware solutions along with the benefits of flexibility, programmability, and ease of verification found with purely software implementations. The processor extensions proposed in this application note give the Xtensa processor a speedup of over 300x compared to a base Xtensa processor or a similar 32-bit RISC engine such as ARM9, MIPS32, etc.

Xtensa Processor Extensions for Data Encryption Standard (DES)

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This application note presents a software implementation of the Data Encryption Standard algorithm using Xtensa processor extensions and describes the methodology used to develop, implement, and debug these extensions. The Tensilica Instruction Extension (TIE) language makes it easy to add the new instructions and configure both the hardware and software environments to use the new instructions.

Xtensa Processor Extensions for Fast IP Packet Classification

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This application note presents how to achieve fast IP packet classification with a configurable processor. Packet classification requires multiple field matching such as the IP source address, IP destination address, source port number, destination port number, protocol number, differentiated service code point (DSCP) and more. To accelerate table lookups and bitmap manipulation, several customized instructions were developed to yield large performance improvements. By using two 200 MHz processors with a proper configuration, OC48 wire-speed packet classification can be achieved while matching on multiple fields with sophisticated rules of ranges and/or prefixes.

Xtensa Processor Extensions for Fast IP Packet Forwarding

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This application note describes how to configure an Xtensa processor to achieve fast IP packet forwarding. By developing three new customized instructions using TIE, the IP table lookup and update functions can be signficantly accelerated. One route lookup can be achieved with less than 10 instructions, compared to more than 100 instructions with a standard RISC processor.

Implementing the Fast Fourier Transform (FFT) for the Xtensa Processor

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The goal of this application note is to show the results and design methodology for a high-performance DSP sample application on the Xtensa microprocessor using a widely known example, the Fast Fourier Transform (FFT). This note first explains the basic algorithm and how several TIE language instructions were created to implement the FFT algorithm. Performance results follow, with a comparison of implementations of the radix-2 decimation-in-frequency FFT with and without additional TIE language extensions.

Accelerating MPEG-4 Video Decoding with an Xtensa Processor

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This application note shows how high-performance implementations can be made for the Inverse Discrete Cosine Transform, variable length decoding and motion compensation using instructions developed in TIE. These optimizations are combined to show that the MoMuSys MPEG-4 reference code can be optimized by a factor of 50. The original code required a processor speed of at least 400 MHz while the optimized code only required 9 mHz without writing any assembly code.

Turbo Coding on Xtensa Processors

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This application note shows how an Xtensa processor can be optimized to handle the performance-intensive signal processing demands of supporting turbo decoding. TIE instructions accelerate turbo decoding by a factor of 95x relative to a base Xtensa processor, enabling decoding of a 2 Mbps channel with a single Xtensa processor.