Xtensa Architecture White Paper

Xtensa Architecture White Paper

Processors have long played an important role in embedded systems design, but fundamental changes in the performance and complexity of those systems are changing that role. Across every embedded application (including data communications, telephony, storage, imaging, and consumer systems), algorithms and protocols are becoming more varied and complex and the data types are growing in richness. In these new systems, a new class of processors is required. Paradoxically, each new processor must fully support the specific new algorithms, datatypes, and bandwidth of its target application, yet must be smaller and more power efficient than traditional processors.

Resolving this paradox requires a new approach to processors - automatic generation of application-specific processors. Tensilica has designed the Xtensa Xplorer design environment and the Xtensa Processor Generator for this purpose. Xtensa Xplorer allows chip architects to rapidly explore alternative design approaches by quickly describing the key instruction, memory, peripheral and interface functions required by their processor. The Xtensa Processor Generator produces a complete processor hardware design, verification and software development environment for that custom processor in minutes. The resulting processor designs consistently execute applications faster, dissipate less power and use less code than general-purpose embedded processors.

The essential foundation of all these processors is the Xtensa Instruction Set Architecture. The base architecture is common to all Xtensa processors. This instruction set was built from the ground up to satisfy the unique requirements of high-performance, high-volume embedded communication and consumer applications. The Xtensa architecture was designed with four key goals:

1. Reduce code size
2. Improve general-purpose embedded processor performance
3. Reduce power dissipation
4. Enable seamless extension of the architecture in support of demanding new applications

Furthermore, it is appropriate today to build a new architectural foundation because of the three dimensions of progress in underlying technology since the emergence of conventional RISC architecture more than fifteen years ago:

• The shift in silicon technology from roughly 3μm to 0.09μm transistor geometry as the "sweet-spot" for implementation
• The shift from general-purpose computing on the desktop to data-centric computing in embedded systems as the primary domain of use.
• Accumulated progress in architectural insights, compilation technology and programming languages and practices.
• The need to reduce power for mobile consumer applications.

This white paper explores the design of that base instruction set architecture and illustrates the impact of architecture on performance using a variety of industry-standard benchmarks. It discusses the trade-offs and innovations required to satisfy all four of the above goals simultaneously. It traces the evolution of modern instruction-set design and compares key features of the Xtensa processor with previous instruction set architectures. It provides a detailed rationale for each major architectural innovation in the Xtensa ISA. Further it introduces the key concepts of instruction set extensibility and briefly illustrates the further dramatic enhancement of performance through application-specific instruction set features.