Using Processors in the SOC Dataplane

Using Processors in the SOC Dataplane

Designers have long understood how to use a single processor for the control functions in an SOC design. However, there are a lot of data-intensive functions that conventional control processors (CPUs) cannot handle. That's why designers have, for a long time now, designed RTL blocks for these challenging functions. However, RTL blocks take a long time to design and verify. Plus they are not programmable and thus not flexible enough to easily handle multiple standards or post-tapeout design changes.

To effectively use processors in the dataplane, designers need a quick, fool-proof way to customize those processors for the exact task at hand. A dataplane processor (or "DPU") naturally connects to existing RTL blocks and provides additional computational horsepower tailored to the exact data type needed - all this with less effort than hand-coding RTL finite state machines or microcoded engines. With a DPU's programmability, designers now have the flexibility to make changes close to and after silicon production. This white paper explains how DPUs can be effectively used in the SOC dataplane.

The SOC Dataplane Challenges

By the mid 1990s, IC manufacturing technology had advanced enough to allow the inclusion of a processor in the standard-cell ASIC along with memory and glue logic. This was the start of the SOC era.

Moore's Law has allowed designers to add more functions to each chip. The main control processors were (and still are) good at executing a wide range of algorithms, but designers often need a lot more performance for major functions such as audio, video, baseband DSP, security, protocol processing, and much more (the list depends on the application). These functions comprise the dataplane of the SOC.

Now the dataplane has become the largest part of an SOC design (see Figure 1), and it certainly takes the longest to design and verify. In most companies, a system architect divides the dataplane tasks into separate teams of engineers, each taking months to design and verify their part of the SOC. Meanwhile, the software team tries to start developing software, but because the hardware isn't designed yet, that's a huge software challenge that often requires significant re-work once the hardware design is completed.

Verilog or VHDL is traditionally used to hand-design digital functions in the dataplane, including functions tightly coupled to conventional CPUs, often referred to as hardware acceleration blocks, or hardware accelerators. Designing this dataplane hardware in RTL takes significant design time, not just for capturing the design intent but for verification of the new hardware. In fact, verification can consume as much as 70-80% of the total hardware design time.

There are two major problems with RTL design:

1. It takes too long to design and verify
2. The resulting hardware is not programmable. All functions are hard wired and can't be easily reprogrammed or changed after the silicon is produced. Most changes require a silicon re-spin.

A Closer Look at RTL Design

Before we can look at alternatives to RTL design, it's important to take a closer look at a typical RTL block. Figure 2 shows the internal structure of a generic RTL block found in an SOC dataplane. The block's datapath appears on the left and its state machine appears on the right.