How to Increase ASICs and SOC Computational Performance with Long-Word Processors

How to Increase ASICs and SOC Computational Performance with Long-Word Processors

VLIW processors execute multiple independent instructions each clock cycle and provide a tremendous performance boost per clock cycle without incurring the exponential power-consumption increase caused by clock-rate increases. However, VLIW architectures have their own problems, particularly code bloat, which causes code footprints to balloon-thus increasing memory costs.

The Xtensa LX processor uses an innovative approach to VLIW design called FLIX (Flexible Length Instruction eXtensions), which gives ASIC and SOC designers more options for cost/performance tradeoffs. FLIX technology provides the flexibility to develop ASIPs (application-specific instruction-set processors) that freely and modelessly intermix smaller RISC instructions with multi-operation FLIX instructions. By packing multiple operations into a wide 32- or 64-bit instruction word, FLIX technology allows ASIC and SOC designers to accelerate a broader class of embedded applications while eliminating the performance and code-size drawbacks of VLIW processor architectures.

One thing's certain in ASIC and SOC design-there's never enough performance to get everything done. ASIC and SOC designers routinely turn to hand-coded RTL acceleration hardware to compensate for the lack of performance they experience with general-purpose, fixed-ISA (instruction-set architecture) processor cores. This is a tired-and-true design approach. However, as ASICs and SOC get larger and larger, the job of verifying all of these custom accelerator blocks has become very cumbersome and the effort needed to verify this hand-coded hardware now dominates most projects.

Some processor-core IP vendors offer superscalar and VLIW architectures that deliver more computing performance per clock cycle, but these architectures also have their limitations. Superscalar processors can only extract so much parallelism from existing code (generally between 2x and 3x) at great hardware cost and VLIW processors use large instruction words that lead to code bloat, which causes code footprints to balloon-thus increasing memory costs. Yet it's desirable to find a way to allow processors to take on more of the computing load on ASICs and SOCs because processors add programmability, hence flexibility, to the chip's design which can be used in several ways.

First, programmability can get the design team out of a jam if product specifications change at the last second (which they often do). Changes can be made without revising the chip's hardware design through a firmware change. Similarly, programmability can also fix that last-minute Algorithm bug-another frequent problem in chip design. Finally, programmability allows more features to be added at a later date, which can extend the life of the hardware design-often called a "mid-life kicker." Features implemented as custom accelerator logic are not changed as easily, so there are many benefits to a more processor-centric approach to ASIC and SOC design, if there's a way to get adequate performance from a firmware-programmable processor.

A Primer on RISC and VLIW Architectures

A processor's instruction-set performance relates to the number of useful operations than can be executed per unit of time or per clock. High performance does not guarantee good flexibility, however. Instruction-set flexibility relates to the wider diversity of different applications whose computations can be efficiently encoded in the instruction stream. A longer instruction word generally allows more operations and operand specifiers to be encoded in each word.