Optimize SOC Performance Using Memory

Optimize SOC Performance Using Memory Tuning and System Simulation

Memory tuning allows you to choose memory-related parameters for each on-chip processor core that balance system performance, processor area (cost), and memory size by exploring a target application's sensitivity to these memory-system parameters. The processor core's instruction-set simulator (ISS) plays a key and central role in this assessment because the ISS can model and report the expected system performance, providing a breakdown of memory-related stalls.

Memory-system configuration requires two phases. First, the SOC design team must establish the strategy for how instructions and data will be stored, answering basic questions such as:

• Will the processor execute its initialization code from off-chip, read-only, or flash memory or will that code be preloaded into a local on-chip instruction RAM? The answer to this question is important because the boot-code location helps determine the kind of memory-bus interface that is required. If the processor never needs access to remote memory except for initialization code, a simpler and smaller memory interface may be appropriate.

• Is the performance-sensitive application code small enough to fit entirely in the processor's local instruction RAM or is an instruction cache necessary? Many design teams automatically assume that cache will be needed when this is not always the case in deeply embedded SOC designs.

• How will the processor load application input data? For example:
  
  
  • Is it loaded from remote input buffers or memories?
  • Is it pushed into the processor's local data RAM by an outside agent such as a DMA controller or another processor?
  • Does the processor directly load the data using input or load instructions?

These questions help determine the kind of memory-bus interface that is required for data transactions.

• How does the output data from the application running on the processor get to other parts of the SOC? For example:
  
  
  • Is it sent to remote output buffers or memories?
  • Is it pulled from the processor's local data RAM by an outside agent such as a DMA controller or another processor?
  • Does the processor transfer the data through direct output operations using output or store instructions?

As with the previous set of questions, these questions also help determine the kind of memory-bus interface that is required for data transactions.

• Can all of the performance-sensitive data (including application data, a maximum-sized stack, and other variable data storage) fit entirely in the processor's local data RAM or will it be necessary to emulate a large local data RAM using a local data cache and a large external memory?