How to Minimize Energy Consumption while Maximizing ASIC and SOC Performance

How to Minimize Energy Consumption while Maximizing ASIC and SOC Performance

Power has become a first-order concern for ASIC and SOC designers right next to performance and area, whether the design is for portable mobile devices, for networking boxes, or for any other application. Optimizing a design for energy at an application and system level has the potential to cut processor and local-memory energy requirements by as much as half in many cases through intelligent design trade-offs. The amount of power savings made at the early architectural level far outweighs any potential power savings that might be made later at the RTL or physical design levels.

There are several EDA design methodologies for reducing ASIC and SOC operating power and energy consumption including clock gating, voltage and frequency reduction, gate sizing and logic optimization, leakage reduction techniques, and low-power libraries and technology processes. Unfortunately, these low-power design methodologies can take months to implement and they still may not reduce power and energy consumption as much as system-level architectural decisions. Architectural decisions are made before any RTL code has been written and it is at that point in the design cycle when the design team has the greatest ability to reduce power and energy consumption.

A lot of emphasis has been placed on guiding ASIC and SOC designers towards performance- and area-optimized architectures with respect to architectural choices such as memory sub-system design (banked memories versus a single large memory), interconnect (single bus versus a hierarchy of buses versus point-to-point interconnects), caches, etc. However, little has been done to guide designers towards the development of energy-efficient system architectures for ASICs and SOCs.

The Xenergy design tool is the industry's first EDA tool to provide a realistic and practical way for hardware designers to quickly estimate the overall energy impact of different processor configurations and extensions. This tool can also help software developers optimize energy-driven application code tuning by running the code on a simulation of the overall processor-plus-memory subsystem. While most software-development tool chains have focused on guiding application-code development to improve performance and code size, Tensilica's Xenergy energy-estimation tool guides designers towards more energy-efficient processor-and-memory sub-system configurations.

Designers can use the Xenergy energy estimator to execute a software application binary on one of Tensilica's Xtensa processor core configuration or a Diamond Standard processor core to get a quick and early estimate of the power and energy consumed by the processor, caches, and local (tightly coupled) memories. The designer can then modify the processor configuration, add instruction extensions, register files, application-specific execution units, or simply tune the application code, with the explicit goal of reducing overall processor and memory energy requirements.

Focus on total energy consumption

A focus on total energy consumption is key to energy-efficient ASIC and SOC design.  Too often, system designers fixate on a static milliwatts-per-megahertz (mw/MHz) power number, ignoring the actual total energy consumption per unit of workload.  This mistake occurs because there's an implicit assumption that roughly equal amounts of work are done each clock period by all processors. This assumption may hold true for general-purpose, 32-bit RISC processors, but it's not a good assumption for task-specific processors such as Tensilica's Xtensa processor, which can be customized for specific on-chip tasks.