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Exploiting Core’s Law
Exploiting Core's Law:
Get "More than Moore" productivity from your ASIC and SOC Design Teams
In 1965, Gordon Moore prophesized that integrated circuit density would double roughly every one to two years. The universal acceptance and relentless tracking of "Moore's Law" set a grueling pace for chip developers. Moore's Law makes transistors ever cheaper and faster (good) while inviting system buyers to expect constant improvements to end-product functionality, battery life, throughput, and cost. The moment a new function is technically feasible, the race is on to deliver it.
Today, it is perfectly feasible to build ASIC devices with more than 100 million transistors, and it won't be long before we see billion-transistor chips that combine processors, memory, logic, and interface components. Designing such chips is an increasingly big challenge. MP ASICs or MPSOCs, multiprocessor SOCs, help you achieve "more than Moore" design productivity gains by leveraging proven IP blocks that give your design team a big head start in the race to design that next killer ASIC.
High ASIC integration creates terrific opportunities. The remarkable characteristics of CMOS silicon scaling allow the cost, size, performance, and power for a given function to all improve simultaneously. This scaling allows continuous end-product improvements: longer battery life, smaller size, more functionality, and better user productivity. ASIC semiconductor scaling has been a key driver for the parallel revolutions in digital consumer electronics, personal computing, and the Internet. Most observers expect this scaling trend to continue for at least another 10 years.
The growth in available on-chip transistors creates a fundamental role for concurrency in ASIC designs. Concurrent tasks such as audio and video processing and network-protocol stack management can operate largely independently of one another. Complex tasks with inherent internal execution parallelism can be decomposed into a tightly-coupled collection of sub-tasks operating in parallel to perform the same work as the original non-parallel task implementation. Such tasks are compositionally concurrent and this kind of concurrency promises significant improvements in application latency, data bandwidth, and energy efficiency when compared to serial execution of the same collection of tasks using a single computational resource. In other words, large numbers of transistors lead to the inclusion of multiple execution engines, which in turn allow design teams to exploit many forms of concurrency that were previously out of reach.
Massive silicon integration presents a terrific opportunity but the associated design task is correspondingly terrifying. Three forces work together to make ASIC design tougher and tougher. Semiconductor manufacturers have had astonishing success in tracking Moore's Law. They truly have given ASIC designers twice as many gates to play with every two years. Second, the continuous improvement in process geometry and circuit characteristics motivates chip builders to design with new IC fabrication technologies as they come available to cut costs and add features. Third, and perhaps most important, the end markets for electronic products-consumer, computing, and communications systems-are in constant churn. System vendors require a constant stream of new functions and performance to justify new consumer purchases.
As a result, the design "hill" keeps getting steeper. Certainly, improved chip-design tools help-faster RTL simulation and verification, higher capacity logic synthesis, and better block placement and routing all mitigate some of the difficulties. Similarly, increasing logic design reuse (IP reuse) reduces the amount of new design that must be done for each chip.
