Diamond Standard Processor Cores

Diamond Standard Processor Cores

A comprehensive family of software-compatible, preconfigured RISC controller cores for your next ASIC or SOC design

Tensilica's Diamond Standard Series is a broad family of preconfigured 32-bit microprocessor and DSP Intellectual Property (IP) cores based on Tensilica's Xtensa Instruction Set Architecture (ISA). All of these code-compatible processor cores employ a common set of software/firmware development tools making it easy for development teams to move from one processor core to another as design needs change or when your design needs multiple cores to execute different tasks. The base Xtensa ISA employs 24-bit, general-purpose RISC instructions that target a wide range of embedded applications. Most common instructions also have a 16-bit narrow encoding to minimize code footprint and the Diamond Series architecture allows modeless switching between 16 and 24-bit instructions. Consequentially, Diamond Standard Series processor cores achieve the highest code densities among all 32-bit RISC processors while delivering industry-leading performance.

Introduction

Tensilica's Diamond Standard Series is a family of code-compatible, preconfigured 32-bit microprocessor and DSP Intellectual Property (IP) cores based on Tensilica's Xtensa Instruction Set Architecture (ISA). The base Xtensa ISA uses 24 bit instructions that target a wide range of embedded applications. Most common instructions in the Xtensa ISA also have 16-bit narrow encodings as well, and the architecture allows modeless switching between 16 and 24-bit instructions so that the compiler is free to pick the smallest possible instruction at any time with no performance penalty. As a result, the Diamond Series processors achieve the highest code densities among all 32-bit RISC processors.

One of the Diamond Standard processors, the 570T high-performance CPU, adds VLIW-style, 64-bit instructions through Tensilica's innovative FLIX (Flexible Length Instruction eXtensions) technology, which allows the processor to issue multiple operations per instruction. These 64-bit instructions are modelessly mixed with the native 16 and 24-bit instructions increase the processor's parallel-execution abilities and further boosts application performance without the code bloat normally associated with VLIW architectures.

This white paper explores the Xtensa instruction set architecture (ISA) and illustrates the impact of processor architecture on performance. It traces the evolution of modern instruction-set design and compares key features of Tensilica's processor architecture with other ISAs. It provides a detailed explanation and rationale for the major architectural innovations in the Xtensa ISA, on which the Diamond Standard Series processor cores are based.

The first section of this white paper gives a quick overview of the Diamond Standard family. The second section outlines the goals, philosophy, and innovations inherent in the Xtensa instruction set. The third section gives a more detailed description, with a block diagram, for each Diamond Standard processor. Finally, the last section gives more information on strength of the Xtensa-based Diamond architecture, taking a look at the superior benchmark performance of the Diamond Standard Series processor cores.

Diamond Standard Family Overview

Tensilica's Diamond Standard processor core family consists of three general-purpose controller cores, a Linux-compatible CPU core, a high-end static superscalar CPU core, a high-performance audio processor core, and a high-end DSP core. Table 1 lists the various Diamond Standard processor cores and gives a quick summary of each core's characteristics.

The Diamond Standard controllers and CPUs are optimized control-plane processors that are industry leaders in area, power consumption, code density and application performance. The Diamond 106Micro and 108Mini enable SOC architects to quickly integrate an efficient CPU into their designs. Both cores are small, low-power 32-bit RISC controllers that achieve the performance levels of much larger, more complex CPUs.

The Diamond 212GP CPU is a small, low-power, high-performance controller core with rich interrupt options and a single-cycle 16x16-bit MAC, which can eliminate the need to include a separate DSP in many system designs. The Diamond 232L adds an MMU (memory-management unit) to support the Linux operating system.

The Diamond 570T is a high-performance, static superscalar processor capable of issuing a 64-bit Very Long Instruction Word (VLIW) bundle consisting of two or three operation slots. The compiler automatically assembles the 64-bit, multiple-operation bundles when it determines that instructions can be issued simultaneously. (The compiler can also create a bundle with just one instruction for performance reasons.) Otherwise, the compiler uses the 16- and 24-bit instructions in the base Xtensa ISA.

This instruction-size flexibility results in very little code expansion from the inclusion of VLIW operations. Normally the ‘no-op padding" required with older, fixed-length VLIW ISAs produces "code bloat" because all instructions in these older VLIW architectures must be the same large (or very large) size. Consequently, the Diamond 570T code density remains high. It is at least 20% better than competing RISC architectures on industry standard benchmarks.