The What, Why and How of Configurable Processors

The What, Why, and How of Customizable Dataplane Processors (DPUs)

Meet performance, cost, and power objectives while reducing the risk of ASIC design and increasing design flexibility

Designers have long understood how to use a single processor for the control functions in a SOC design. However, there are a lot of data-intensive functions that control processors cannot handle. That's why designers design RTL blocks for these functions. However, RTL blocks take a long time to design and even longer to verify, and they are not programmable to handle multiple standard or designs.

Dataplane processors (DPUs) are designed to provide programmability in the performance-intensive dataplane of the SOC design. You can think of them as a combination of a DSP and a CPU - but they're even better than that, as you can customize them for maximum efficiency for your target application. Need wide datapaths or instructions? Read more about how you can quickly get these built into your own DPU.

What is a DPU? What can DPUs do? Why would anyone want to use this type of processor? How can a DPU be used instead of creating hand-coded RTL hardware? These questions and more are answered in this white paper.

The most common embedded microprocessor architectures-such as the ARM, MIPS, and PowerPC processors-were developed in the 1980s for stand-alone microprocessor chips. These general-purpose processor architectures, commonly called CPUs, are good at executing a wide range of algorithms with a focus on control code, but SOC designers often need more performance in critical datapath portions of their designs than these microprocessor architectures can deliver.

Two approaches most often used to bridge this performance gap are to run the general-purpose processor at a higher clock rate (thus extracting more performance from the same processor architecture) or to hand-design acceleration hardware that removes some of the processing burden from the processor. Running a general-purpose processor core at a high clock rate incurs a power penalty and designing acceleration hardware takes additional design time, not just for the design but for verification of the new acceleration hardware. In fact, verification can consume as much as 70-80% of the total design time. Let's examine these two familiar performance-boosting alternatives in more depth.