Optimizing a DSP Architecture for Wireless Baseband - The high computation demands of next-generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. New DSP architectures are needed for applications with heavy workloads with complex filtering, FFT, and MIMO matrix operations.
Everything You Wanted to Know About Blu-ray Audio, but were afraid to hear - Although Blu-ray discs look physically like DVDs, there are many differences including many differences in the audio. This white paper discusses those differences and the design issues surrounding the development of audio subsystems for Blu-ray disc players and related equipment.
UPDATED How to Manage Video Frame Processing Time Deviations in ASIC and SOC Video Processors - HD video encoding and decoding algorithms get the bulk of attention by designers developing such products, but HD video codecs for advanced video applications such as broadcast television and Blu-ray disc players have quickly become standardized; there’s little room for product differentiation in a standardized video codec. However, you can substantially differentiate an HD product’s design by improving the video image stream—both before video compression and after.
Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC - This paper explains the benefits of using a programmable processor-based solution for audio processing in SOC designs, as well as the disadvantages of using a RISC or other general-purpose core. It explains the 300 audio-specific instructions added to make the HiFi 2 Audio DSP much more efficient than a standard RISC processor to handle audio processing tasks.
How to Add Low-Power, Multi-Codec Digital Video and Audio to Your Next ASIC or SOC Design - this white paper reviews digital video compression basic including the different types of algorithms used, a simple block diagram of the steps required for video compression and decompression, elements of a hardware video processors, task allocation for H.264 decoding, how to pass information to and from a video processor, and what a SOC design using a video processor might look like.
NEWSeven Critical Questions to Ask When Selecting a Digital Audio Solution for Your Next Mobile SOC Design - The complexity of delivering a mobile audio IP solution to SOC designers causes design teams to ask many, many questions before choosing an audio core and associated codecs. That's a good thing. The selection process is complex, and the more information you have before making the decision, the better. Experience shows that design teams' questions about mobile audio solutions fall into seven broad categories.
BASIC INFORMATION
Using Processors in the SOC Dataplane - To effectively use processors in the dataplane, designers need a quick, fool-proof way to customize those processors for the exact task at hand. A dataplane processor (or "DPU") naturally connects to existing RTL blocks and provides additional computational horsepower tailored to the exact data type needed - all this with less effort than hand-coding RTL finite state machines or microcoded engines.
The What, Why and How of Customizable Dataplane Processors (DPUs) - What is a DPU? What can DPUs do? Why would anyone want to use this type of processor? How can a DPU be used instead of creating hand-coded RTL hardware? These questions and more are answered in this white paper.
10 Reasons to Customize a Processor Core - If you have more than simple control tasks, we give you ten good reasons why you should consider customizing your core in your next SOC design.
Xtensa Architecture White Paper -Find out more about the great modern architecture behind all of Tensilica's processor cores and why it helps deliver the lowest power and highest performance and code density in the industry.
Exploiting Core's Law: Get "More than Moore" Productivity From your ASIC and SOC Design Teams - While it is feasible to build ASIC devices with more than 100 million transistors, designing these chips is a big challenge. Programmability vs efficiency trade-offs are examined, and suggestions are made for an improved ASIC design methodology using processors as basic building blocks.
10 Tips for Successful SOC Design - SOC designs are major projects. They can produce high-volume, immensely profitable chips but not without risk, as is true for any big project. Most SOC design projects do not complete on time or on budget. Too many are not completed at all. Although there is some risk involved, the rewards for success are great. These 10 tips will help your team find the path to a successful SOC design.
UPDATEDEverything You wanted to Know About SOC Memory* But were Afraid to Ask - If you are a member of an SOC design team, or if you manage one, then memory is critically important to you. On today's multicore SOC designs, more on-chip silicon is devoted to memory than to anything else on the chip and yet memory is often added as an afterthought. Don't let that happen to your team.
A Processor and DSP IP Selection Checklist - SOC designs are major, high-risk projects and most consist of many IP blocks-some developed in house and some purchased. Many of the most complex blocks are processors and DSPs. With their associated software-development tools, simulation models, and EDA flow scripts, these processor IP blocks can literally make or break your project. Here is a list of questions to ask yourself, your team, and any processor IP providers you contact.
TIE - The Fast Path to High-Performance Embedded SOC Processing - TIE, Tensilica’s Instruction Extension language, is a simple way to make Xtensa processor cores faster and more efficient by adding new task-optimized instructions and I/O interfaces.TIE looks a lot like Verilog, but anyone can learn the basics of TIE in a few minutes whether they already know how to write Verilog descriptions or not. Just a few lines of TIE can make a dramatic difference in an Xtensa processor’s performance and flexibility for targeted tasks. Xtensa processors with TIE customizations can compute and move data tens or hundreds of times faster than conventional processor cores. As a result, your SOC gets smaller, cheaper, and faster and it will consume less power.
NEWOptimize SOC Performance Using Memory Tuning and System Simulation - Memory tuning lets you choose memory-related parameters for each on-chip processor core to balance system performance, processor area, and memory size by exploring a target application's sensitivity to these memory system issues.
How to Increase ASICs and SOC Computational Performance with Long-Word Processors - By packing multiple operations into a wide 32- or 64-bit instruction word, FLIX technology allows designers to accelerate a broader class of “hot spots" in embedded applications while eliminating the performance and code-size drawbacks of VLIW processor architectures.
UPDATED How to Minimize Energy Consumption while Maximizing ASIC and SOC Performance - The Xenergy tool is the first tool that provides a realistic way to estimate the overall energy impact of different processor configurations and extensions. It also helps software developers with energy-driven application code tuning on the overall processor plus memory subsystem.
