White Papers

BASIC INFORMATION

• Using Processors in the SOC Dataplane - To effectively use processors in the dataplane, designers need a quick, fool-proof way to customize those processors for the exact task at hand. A dataplane processor (or "DPU") naturally connects to existing RTL blocks and provides additional computational horsepower tailored to the exact data type needed - all this with less effort than hand-coding RTL finite state machines or microcoded engines.
• The What, Why and How of Configurable Processors - What is a configurable processor? What can configurable processors do? Why would anyone want to use this type of processor? How can a configurable processor replace RTL coding? How does an engineer design with configurable processors?
• Xtensa Architecture White Paper -Find out more about the great modern architecture behind all of Tensilica's processor cores and why it helps deliver the lowest power and highest performance and code density in the industry.
• Why High MHz Does Not Mean High Performance - Traditionally, performance has been associated with higher frequency. However, higher performance can be achieved even while running the processor at lower frequency. This leads to not only lower power, but also to better architecture-performance efficiency and lower area. This lower area in turn leads to even more power savings when compared to traditional deep-pipeline RISC processors.
• Exploiting Core's Law: Get "More than Moore" Productivity From your ASIC and SOC Design Teams - While it is feasible to build ASIC devices with more than 100 million transistors, designing these chips is a big challenge. Programmability vs efficiency trade-offs are examined, and suggestions are made for an improved ASIC design methodology using processors as basic building blocks.
• Processor Core Customization: Your SOC design team’s fastest route from C to gates - A manager’s quick guide to leading your SOC design team out of verification Hell and toward a successful first-time tapeout.
• How to Avoid the Traps and Pitfalls of SOC Design - Chances are pretty good that your current SOC design approach is making your job much harder than it needs to be.
• New 10 Tips for Successful SOC Design - SOC designs are major projects. They can produce high-volume, immensely profitable chips but not without risk, as is true for any big project. Most SOC design projects do not complete on time or on budget. Too many are not completed at all. Although there is some risk involved, the rewards for success are great. These 10 tips will help your team find the path to a successful SOC design.
• Everything You wanted to Know About SOC Memory* But were Afraid to Ask - If you are a member of an SOC design team, or if you manage one, then memory is critically important to you. On today's multicore SOC designs, more on-chip silicon is devoted to memory than to anything else on the chip and yet memory is often added as an afterthought. Don't let that happen to your team.
• New A Processor and DSP IP Selection Checklist - SOC designs are major, high-risk projects and most consist of many IP blocks-some developed in house and some purchased. Many of the most complex blocks are processors and DSPs. With their associated software-development tools, simulation models, and EDA flow scripts, these processor IP blocks can literally make or break your project. Here is a list of questions to ask yourself, your team, and any processor IP providers you contact.
• TIE - The Fast Path to High-Performance Embedded SOC Processing - TIE, Tensilica’s Instruction Extension language, is a simple way to make Xtensa processor cores faster and more efficient by adding new task-optimized instructions and I/O interfaces.TIE looks a lot like Verilog, but anyone can learn the basics of TIE in a few minutes whether they already know how to write Verilog descriptions or not. Just a few lines of TIE can make a dramatic difference in an Xtensa processor’s performance and flexibility for targeted tasks. Xtensa processors with TIE customizations can compute and move data tens or hundreds of times faster than conventional processor cores. As a result, your SOC gets smaller, cheaper, and faster and it will consume less power.

DIAMOND STANDARD PROCESSOR CORES

• Diamond Standard Core Family - An overview of this upward compatible family of efficient 32-bit RISC CPUs.

XPRES C-to-RTL COMPILER

• Boost ASIC and SOC Performance by Matching Processor to Task Through Automated Processor Generation - This white paper explains the major decisions in architecting an SOC and guides the designer to a systematic approach to design structure using processors as the fundamental building blocks of the SOC.

XTENSA LX

• Minimize Energy Consumption While Maximizing ASIC and SOC Performance - The Xenergy tool is the first tool that provides a realistic way to estimate the overall energy impact of different processor configurations and extensions. It also helps software developers with energy-driven application code tuning on the overall processor plus memory subsystem.
• How to Increase ASICs and SOC Computational Performance with Long-Word Processors - By packing multiple operations into a wide 32- or 64-bit instruction word, FLIX technology allows designers to accelerate a broader class of “hot spots" in embedded applications while eliminating the performance and code-size drawbacks of VLIW processor architectures.
• Processor Ports and Queues: Easily Overcome I/O Bandwidth Obstacles in Your Next ASIC or SOC Design - Wire-based interfaces are familiar to many RTL designers and allow Tensilica's processors to substitute for hardware blocks without even changing the block-interface (“pin") definitions of existing RTL blocks.
• Get Your ASICs and SOCs off the Bus! - This paper describes the most common hardware mechanisms - buses, direct connections, and data queues - used to interconnect processor cores on ASICs. It explains how direct processor-to-processor connections reduce the cost and latency of inter-processor communications.

LOW POWER

• Processor Core Power Specs: A Cautionary Tale - It's what they don't tell you about power specs that matter.
• How to Minimize Energy Consumption while Maximizing ASIC and SOC Performance - The Xenergy tool is the first tool that provides a realistic way to estimate the overall energy impact of different processor configurations and extensions. It also helps software developers with energy-driven application code tuning on the overall processor plus memory subsystem.

DSP

• New Cut DSP Development Time - Get High Performance From C, No Assembly Required - The magic is in the compiler technology. Learn how an advanced compiler can help you get equivalent or better performance using standard C than other DSPs programmed in assembly code.
• Tensilica Xtensa LX Processor with Vectra LX By BDTI - this BDTI report evaluates the highest performance DSP core BDTI has tested.
• NewOptimizing a DSP Architecture for Wireless Baseband - The high computation demands of next-generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. New DSP architectures are needed for applications with heavy workloads with complex filtering, FFT, and MIMO matrix operations.
• New The Five Pitfalls of 4G Baseband SOC Design - As Tensilica has been working with its customers to design building blocks for LTE PHY designs, including the DSPs and forward-error-correction subsystems, we've realized five key pitfalls associated with LTE baseband development.

AUDIO/VIDEO

• New Everything You Wanted to Know About Blu-ray Audio, but were afraid to hear - Although Blu-ray discs look physically like DVDs, there are many differences including many differences in the audio. This white paper discusses those differences and the design issues surrounding the development of audio subsystems for Blu-ray disc players and related equipment.
• A Designer’s Guide to HD Video Pre- and Post-Processing - HD video encoding and decoding algorithms get the bulk of attention by designers developing such products, but HD video codecs for advanced video applications such as broadcast television and Blu-ray disc players have quickly become standardized; there’s little room for product differentiation in a standardized video codec. However, you can substantially differentiate an HD product’s design by improving the video image stream—both before video compression and after.
• Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC - This paper explains the benefits of using a programmable processor-based solution for audio processing in SOC designs, as well as the disadvantages of using a RISC or other general-purpose core. It explains the 300 audio-specific instructions added to make the HiFi 2 Audio DSP much more efficient than a standard RISC processor to handle audio processing tasks.
• How to Add Low-Power, Multi-Codec Digital Video and Audio to Your Next ASIC or SOC Design - this white paper reviews digital video compression basic including the different types of algorithms used, a simple block diagram of the steps required for video compression and decompression, elements of a hardware video processors, task allocation for H.264 decoding, how to pass information to and from a video processor, and what a SOC design using a video processor might look like.