Xtensa 9 Microprocessor Data Book

Xtensa 9 Microprocessor Data Book

The Xtensa 9 processor is a configurable, extensible, and synthesiable 32-bit RISC processor core, which is extremely versatile for control-plane and data-plane SOC applications. X8 processor features include:

• 32-bit synthesizable RISC architecture with 5-stage pipeline, 16/24-bit instruction encoding with modeless switching
• Designer-configurable processor options (MMU/MPU, local memory types and sizes, hardware multipliers, etc.)
• Optional designer-defined application-specific instructions can be added to the base architecture
• Automated fine and coarse-grain clock gating for ultra-low power
• Innovative flexible I/Os that bypass the main system bus
• Local memories can include parity or ECC.

This manual describes all aspects of the Xtensa 9 processor.