The μDMA engine is a closely coupled chaining DMA with interleaved 3D transfers that is closely coupled to the IVP core to reduce DMA programming and completion overhead. It has autonomous parallel operations with an independent 512-bit/cycle memory port into local data memory and a 128-bit/cycle port onto the AXI bus. It eliminates memory latency for loads and stores. It offers up to 10 GBytes/second of throughput to keep up with the rapid pace of resolution and frame rate requirements.

Optional port connections to legacy RTL blocks let designers stream data and control between the IVP core and the RTL blocks without having to go through memory.

The memory/network interface combines the IVP core and micro-DMA transactions with cluster traffic.

The IVP is highly energy efficient compared to CPUs or GPUs for 16-bit pixel operations (e.g., absolute-difference, multiply-add, shift-saturate). As an example, for IVP implemented in an automatic synthesis, place-and-route flow in 28nm HPM process, regular Vt, a 32-bit integral image computation on 16b pixel data at 1080p30 consumes 10.8 mW. The integral image function is commonly used in applications such as face and object detection and gesture recognition.

IVP’s high performance is demonstrated by complex kernels such as motion search and normalized cross-correlation, commonly used in high-precision block and feature matching and optical flow. For a smart motion search on 16-bit data over a 1920x1080 frame with 256x16 pixel search range and 9x3 pixel block size, IVP can achieve a rate of 142 sums of absolute differences per cycle. a normalized cross-correlation function on 16-bit pixel data with 32-bit accuracy achieves 1 million 8x8 blocks per second.

The IVP core is based on our proven Xtensa architecture. It uses a 4-way instruction issue with up to three pixel arithmetic operations per cycle (MUL, MAC, select, shift, ALU). It is capable of two 512-bit (32x16-bit) pixel data memory references per cycle.  It features a 32-way vector SIMD with 16-bit register elements. It employs 8– and 16-bit memory elements. And its instruction set is further extensible by the designer.

Each SIMD slide contains a rich set of computations resources:

• 3 independent 16-bit ALUs, 16x16 multiplier, 16-bit variable shifter
• 3 register files per slide (pixel register file, predicate register file and shift select register file)
• Interface to memory system that loads 8- or 16-bit data
• Cross-element select and reduction network for arbitrary number of element swaps or reduction of operations per cycle (e.g. reduction min-max, reduction adds)
• Memory rotator that operates at full rate on data from or to unaligned structures
• Prediction fully supported by compiler for high utilization

The 4-way VLIW issue of vector operations gives an almost arbitrary mix of loads, stores, multiplies, and three ALU operations all taking place simultaneously across all 32 element engines.

The IVP features many imaging-specific operations to accelerate 8-, 16- and 32-pixel data types and video operation patterns.