Xtensa XTMP and XTSC

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Xtensa Processor Developer's Toolkit Product Brief

Xtensa Software Developer's Toolkit Product Brief

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TIE - The Fast Path to High-Performance Embedded SOC Processing

Optimize SOC Performance Using Memory Tuning and System Simulation

Avoid Bus Bottlenecks and Get More Performance from your ASIC and SOC Designs by Using High-Speed On-Chip I/O

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The XTensa Modeling Protocol (XTMP) and XTensa SystemC Modeling (XTSC) for Fast System Modeling and Simulation

Plus Pin-Level XTSC Allows Co-Simulation with Verilog

Many SOC designs today employ multiple processors.  As SOC design becomes more complex, new methods to describe, debug and profile overall system performance need to be employed. Unfortunately, most software development tools vendors do not provide pre-silicon simulation environments for multiple processor SOCs.  Tensilica offers two modeling tools: XTMP (XTensa Modeling Protocol) for modeling in C and XTSC (XTensa SystemC) for modeling in SystemC. XTSC offers co-simulation with Verilog using its pin-level modeling capabilities (see below).

Both tools are powerful additions to Tensilica's software development toolkit. They provide an Application Programming Interface (API) to the ISS, allowing fast and accurate simulation of SOC designs incorporating one or more processor cores. Running up to 100 times faster than RTL simulators, the XTMP/XTSC environments are potent tools for software development and SOC design.  Both tools give you the ability to rapidly explore SOC partitioning alternatives and HW/SW performance tradeoffs.

XTMP/XTSC are used for simulating homogeneous or heterogeneous multiple processor design subsystems as well as complex uni-processor architectures. Use Xplorer's multi-processor project to instantiate multiple processor subsystems (or do it manually) and optionally connect them to custom defined peripherals and interconnects. You can create, debug, profile and verify combined SOC and software architectures early in the design process. As the simulator operates at a higher level than HDL simulations, simulation time is cut drastically.

Using the ISS with XTMP or XTSC for modeling

XTMP/XTSC are integrated into the Xtensa Xplorer IDE, which automates the creation and development of multiple processor subsystem simulations.  For XTMP, simulations are described in standard C code, which you can modify to allow more complex systems and additional simulator control if required.  For XTSC, simulations are described in standard SystemC code. In addition, you have full visibility into all aspects of the simulation through the extensive API.  Separate debuggers can be connected to each simulated core for additional visibility.

Modeling of Local and System Memory

XTMP and XTSC allow memory modeling of both local and system memory. System memory can have programmable latencies specified for different transaction types, allowing an accurate system simulation for analyzing performance tradeoffs. Memory-mapped peripherals may be included in an XTMP/XTSC system simulation, and functions are provided to connect the DPU to peripheral devices.

A Multi-threaded Environment

An XTMP or XTSC simulation runs in a multi-threaded environment, with each processor running in its own thread. A separate debugger is connected to each core for full visibility, and core threads can be run asynchronously or synchronized through events. Another option is to run all cores in lock-step, cycle-by-cycle mode. If one core stops on a break, all cores stop until it resumes. XTMP and XTSC have many of options for implementing, controlling and displaying results of system simulations deploying multiple cores, memories, and user-defined devices.

Pin-Level SystemC CoSimulation with Verilog

Additionally, Tensilica provides a link between its pipeline-accurate, cycle-accurate ISS and the leading Verilog simulators. Designers can now run pin-level SystemC co-simulations of Tensilica DPUs in their native Verilog simulators with pin-level XTSC.

With its pin-level modeling capabilities, XTSC allows co-simulation with Verilog

XTMP provides a simulation environment using instantiations of multiple processor capable ISS, memory models and connectors

Using the Xtensa ISS and TurboXim with the XTMP or XTSC Environment in Your SOC Design: