Xtensa Software Developer's Toolkit

Advanced Software Development Tools for Tensilica’s Processors

Features

• Xtensa Xplorer Integrated Development Environment (IDE) with full graphical user interface (GUI)
• Mature optimizing XCC C/C++ Compiler
• Operator overloading support in C for custom data types
• Pipeline-modeling, cycle-accurate Instruction Set Simulator (ISS)
• GNU profiler, linker, debugger, assembler and utilities
• Multiple processor subsystem simulation, debug, profiling and memory partitioning
• Project management tools
• Performance and energy analysis tools
• Support for several operating systems such as Embedded Alley, Express Logic, open-source Linux, Mentor Graphics, Sophia Systems uITRON, and Timesys.

Benefits

• Easy to use Xplorer IDE based on familiar Eclipse platform
• Small, high-performance code from 'C' source
• Compiler offers state-of-the-art inter-procedural and alias analysis
• Automatic vectorization of operations for Xtensa SIMD processors
• Automatic FLIX instruction bundling for multi-issue Xtensa VLIW cores
• Detailed pipeline analysis guides optimizations from cycle/pipeline-accurate instruction set simulator (ISS)
• Easily and quickly evaluate multiple processor subsystems
• Familiar GNU-based toolchain

Tensilica's Eclipse-based Xtensa Xplorer IDE serves as the cockpit for software development

If you need to develop application code for an Xtensa processor, the Xtensa Software Developer's Toolkit provides a comprehensive collection of code generation and analysis tools that speed the development process. Tensilica's Eclipse-based Xtensa Xplorer Integrated Development Environment (IDE) serves as the cockpit for the entire development experience. If you are a custom Xtensa processor developer, you will use the \'Xtensa Processor Developer\'s, in addition to using the Xtensa Software Developer's Toolkit.

The Xtensa software development environment is automatically generated from the same database as the processor hardware description. All configuration options and designer-defined TIE (Tensilica Instruction Extensions) are supported. There is no need to manually edit or extend the tools to match these options. There is no chance that a software engineer implementing a new instruction in the compiler will implement the instruction differently than the hardware engineer who wrote the instruction because there is only one unified source description. This approach assures correctness and consistency by construction. See Figure 1.

Designers get a compiler, linker, assembler, and debugger for their particular processor hardware. As the base ISA is always present, third party tools can still be used even when the core is customized for a particular application.

Shorter Development Times for Software and Hardware Designers

Within the single IDE, software developers create simpler, more portable and maintainable code with operator overloading on custom datatypes as well as reducing debug time with user-defined display formats.

Hardware developers create multiple-core subsystems in minutes for evaluation and load profiling in simulation. All developers benefit from faster simulations in the ISS and SystemC.

Robust Infrastructure Support

Configurability of a Tensilica processor core never compromises the underlying base Xtensa instruction set, thereby ensuring availability of a robust ecosystem of third party application software and development tools. All configurable, extensible Xtensa processors are always compatible with major operating systems, debug probes and ICE solutions and always come with an automatically generated, complete software development toolchain including an advanced integrated development environment based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry-standard GNU toolchain.